Bedrock

Bedrock

A 64-bit instruction set architecture and systems-software specification. It has variable-length encoding, restartable repeated instructions, and an optional scalable-vector extension.

Encode intent. Decompose execution. Why Bedrock →

Under active design. Encodings, ABIs, and tool interfaces may change.

01Encoding

Opcode spaceEncodingsExample
1Bextrashort2500000101SYSCALL
2Bshort421000001zsdADD.{L|Q}(z) Rn(s), Rn(d)
3Bmedium17711L00111zddeLEA.{B|W|L|Q}(z) <ea>(e), Rn(d)
4Blong25411L111101000000zcsdCMPJcc.{B|W|L|Q}(z) Rn(s), Rn(d), <imm8s>
5Bextralong16611L111111011100z0ppvwwyVFMADD.{H|S|D}(z) Pn(p), Vn(v), Vn(w), Vn(y)
6Bxxlong13311L1111111100000010000x0011pvveVFADD.{H|S|D}(x) Pn(p), <ea>(e), Vn(v)

797 encodings across 385 instructions, read from the specification sources at build time. The first one or two bytes give the instruction's length; displacements, immediates, and other payloads follow the opcode space, up to 18 bytes in total. In the examples, the bold leading bits are the header framing, L is the length field of extended instructions, digits are fixed opcode bits, letters are operand fields, and thick rules mark byte boundaries.

02Specification

03Microarchitectures

  1. H1Talc
  2. H2Gypsum
  3. H3Calcite
  4. H4Fluorite
  5. H5Apatite
  6. H6Orthoclase
  7. H7Quartz
  8. H8Topaz
  9. H9Corundum
  10. H10Diamond

Designs are graded H1 to H10 on the Mohs scale by overall design intensity. Bedrock Calcite (H3, scalar in-order) is the current design; H7 to H10 are named but undefined until there are real designs to place there.

04Roadmap

  1. Foundation
    • Architecture
    • ABI
    • Sail model
    • LLVM toolchain
    • Emulator
  2. Platform foundation
    • Subsystem interface
    • Discovery
    • Architectural timer
  3. Platform profiles
    • Interrupts
    • IOMMU
    • Power & clock
    • Reset
    • PCIe
  4. General-purpose platform
    • Minimum platform profile
  5. Standard bindings
    • UEFI
    • ACPI
  6. 1.0
    • Stable contract

Contracts are closed in dependency order. There is no published schedule.

05Repositories

specISA, ABI, compiler interface, Sail model, generated artifacts, emulator, samples
llvm-projectBedrock targets for LLVM, Clang, LLD, and related tools
microarch-*One microarchitecture each: RTL, verification, design-local docs