Bedrock

Why Bedrock

Encode intent.
Decompose execution.

A Bedrock instruction can carry a whole loop. The processor splits it into internal steps using a fixed template for that instruction, instead of rebuilding the loop from many small instructions.

01memcmp in one instruction

memcmp(a, b, n)

REPEQ R2, CMP.B [R0++], [R1++]
  1. load a byte from [R0]
  2. load a byte from [R1]
  3. compare them
  4. advance R0 and R1, decrement R2
  5. stop if they differ or R2 is zero

This is all of memcmp: one instruction, with R0 and R1 pointing at the two buffers and R2 holding the length. The pointers advance through the [R0++] addressing form, so there is no separate increment, compare, or branch. Each iteration commits on its own, and if an interrupt arrives partway through, R0, R1 and R2 already hold the progress. Returning to the same instruction continues from there.

The project calls this style DISC, for decomposition-oriented instruction set computer. The core receives the whole loop as one instruction and splits each iteration into the listed steps from a fixed template.

02Rules that follow from it

Length
Instructions are 1 to 18 bytes long. The first one or two bytes give the length, so the decoder knows where the next instruction starts before it looks at any operand.
Commit
An instruction becomes visible all at once, however many internal steps it takes. A repeated instruction does this once per iteration.
Interrupted work
Repeated instructions and vector gather/scatter can stop partway. Their progress is in their own operands, such as the counter and pointers in the memcmp example, so running the same instruction again finishes the rest.
Implementations
A small core can run the internal steps one at a time. A wide core can run independent steps in parallel. Both implement the same instruction.

03History

  1. May 2026

    First commit. Compound instructions were already split into internal steps, but the rest looked like a cleaned-up CISC: separate data and address registers, modifier prefixes, and hidden state for resuming repeated instructions.

  2. July 2026

    The encoding was redone so every instruction states its own length. The register file became R0 to R15, and interrupts and exceptions moved to one event model.

  3. August 2026

    The decoder started being generated from the specification, including a SystemVerilog version. The hidden resume state was removed; an interrupted repeat now restarts by decoding its prefix again.

The rules in the previous section describe the design as it stood after these changes. The longer rationale is in spec#4.