C Memory Model

This section defines how the baseline C memory model maps to Bedrock memory operations and ordering instructions.

The ISA memory model owns access atomicity, alignment, instruction-order selectors, and the global sequentially consistent order. This C ABI owns atomic-object eligibility and the lowering of C operations into those ISA contracts.

Atomic Object Eligibility

The native lock-free set consists of integer objects and ordinary 64-bit pointer objects whose size is 1, 2, 4, or 8 bytes and whose address satisfies the natural alignment for that size. An unaligned atomic object requires the target constraint diagnostic below. Accordingly, __atomic_always_lock_free returns true only for those naturally aligned sizes.

The baseline accepts an atomic object only when it belongs to that native lock-free set. Any other atomic object—including a floating-point, aggregate, 128-bit integer, unsupported-width, or insufficiently aligned object—is a target constraint violation.

Native Atomic Primitives

Once the object satisfies the width and alignment requirements above, the compiler uses the following primitive lowering. The ordering sequences are defined separately below.

Native Atomic Primitive Quick Reference

C operation	Bedrock lowering
atomic_load	aligned MOV access plus the order sequence
atomic_store	aligned MOV access plus the order sequence
atomic_compare_exchange	CMPXCHG
atomic_exchange	loop using CMPXCHG

C Atomic Memory Order Mapping

C Atomic Memory Order Mapping

C order	Instruction	Load	Store	Fence
relaxed	relaxed	load	store	zero instructions
consume	acquire	load; AFENCE	—	AFENCE
acquire	acquire	load; AFENCE	—	AFENCE
release	release	—	AFENCE; store	AFENCE
acq_rel	acqrel	—	—	AFENCE
seq_cst	seqcst	AFENCE; load; AFENCE	AFENCE; store; AFENCE	AFENCE

For C compare-exchange, the compiler selects the join of the success and failure orders through the order lattice, independently of their numeric encodings. Consume is treated as acquire, acquire joined with release is acquire-release, and sequential consistency dominates every other order. A failure performs a read-only operation. Release-sequence effects arise from successful writes, while a failed CMPXCHG.SEQCST still participates in the global SC order as an SC load.

The relaxed C thread fence emits a zero-instruction sequence. Consume, acquire, release, acquire-release, and sequentially consistent thread fences emit AFENCE.

Volatile, Device, and Executable Memory

Volatile accesses preserve the observable access count and order. C atomic operations and fences provide the inter-thread ordering defined above. The C target interface owns the executable-byte publication operation. A relocation agent completes that operation before transferring control to patched instructions.

C Fetch RMW Lowering

C Fetch RMW Lowering

C operation	Bedrock lowering
atomic_fetch_add	FETCHADD
atomic_fetch_sub	FETCHSUB
atomic_fetch_and	FETCHAND
atomic_fetch_or	FETCHOR
atomic_fetch_xor	FETCHXOR