Data Formats

Integer Data Sizes

Integer operands use size suffixes to select the low-order subfield of an Rn register and the number of bytes transferred by memory operands.

Byte, word, and long operations use the low-order subfield of the selected register. Q-sized operations use the full 64-bit register.

Every Rn destination write defines all 64 bits. A Q-sized write uses the complete result. For a B-, W-, or L-sized write, ABS, DIVS, MODS, DIVMODS, MINS, MAXS, SAR, and the explicit EXTS operations sign-extend the selected-width result to 64 bits. Every other integer operation, including MOV, neutral modular arithmetic, logical and bit operations, count and Boolean results, address results, atomic return values, and state-register reads, zero-extends the selected-width result to 64 bits. This result extension does not change FLAGS calculation, which continues to use the selected operation size.

Memory destination writes transfer only the selected number of bytes. Extension-store instructions instead write the explicitly named W, L, or Q destination width. SP has only Q-sized writable forms. The result-extension rule applies to Rn destinations.

Integer Data Sizes

Code	Suffix	Bits	Bytes	Name
B	.B	8	1	Byte
W	.W	16	2	Word
L	.L	32	4	Long
Q	.Q	64	8	Quad

Rn Register Operand Subfields

Little-Endian Memory Organization

Integer data, immediates, displacements, and absolute address payloads are little-endian. Multi-byte numeric payloads are stored least significant byte first. The decoder consumes instruction-header fields byte by byte in instruction-stream order.

For an N-byte integer value stored at byte address A, byte A contains bits 7..0, byte A+1 contains bits 15..8, and so on.

Little-Endian Byte Order for a 64-Bit Value

Instruction Start Bytes

H0 and H1 denote header bytes 0 and 1; H1 belongs to the header only for medium and longer instructions.

Floating-Point Data Formats

Floating-Point Scalar Sizes

Code	Suffix	Bits	Bytes	Name
H	.H	16	2	Half (conversion and storage)
S	.S	32	4	Single
D	.D	64	8	Double

Floating-point scalar formats are little-endian in memory as well. H is IEEE-754 binary16 with 11 bits of significand precision, minimum normal exponent \(-14\), and minimum subnormal quantum \(2^{-24}\). H is available to the scalar instruction set only as a conversion and storage format; scalar arithmetic remains S/D. S is IEEE-754 binary32 with 24 bits of significand precision, minimum normal exponent \(-126\), and minimum subnormal quantum \(2^{-149}\). D is IEEE-754 binary64 with 53 bits of significand precision, minimum normal exponent \(-1022\), and minimum subnormal quantum \(2^{-1074}\).

Floating-Point Register Encodings

For a NaN, the most significant fraction bit is the quiet bit: bit 22 for S and bit 51 for D. s denotes the sign bit. An S result occupies Fn bits 31..0 and writes zero to Fn bits 63..32.

The bit-level floating-point encoding, NaN policy, exception flags, and rounding behavior are defined by the floating-point instruction and state descriptions; their memory byte order follows the same least-significant-byte-first rule as integer data.