VTRNLO

Operation

Interleave even lanes from the old destination and source by adjacent result pairs.

Assembler Syntax

VTRNLO.{B|W|L|Q}(z) Pn(p), Vn(v), Vn(w)

Privilege

Unprivileged

Required CPUID flags

VECTOR

For each adjacent result-lane pair, VTRNLO selects the even lane of the corresponding pair in both inputs. The even result lane receives that old destination value, and the odd result lane receives the value from Vn. The governing predicate retains the corresponding old destination value in each inactive result lane.

At W width, each active even result lane receives the selected even old-Vd lane and each active odd result lane receives the matching even source-Vn lane; inactive result lanes preserve old Vd.

VTRNLO.W even-lane transpose

2.75in

Encodings

VTRNLO.{B|W|L|Q}(z) Pn(p), Vn(v), Vn(w)

Format: Instruction format for VTRNLO.{B|W|L|Q}(z) Pn(p), Vn(v), Vn(w)

Format: Instruction format for VTRNLO.{B|W|L|Q}(z) Pn(p), Vn(v), Vn(w)