VREDMINS

Operation

Finds the signed minimum of selected integer lanes and writes the scalar result to Rn.

Assembler Syntax

VREDMINS.{B|W|L|Q}(z) Pn(p), Vn(v), Rn(r)

VREDMINS.{B|W|L|Q}(z) Pn(p), <ea>(e), Rn(r)

Privilege

Unprivileged

Required CPUID flags

VECTOR

The governing predicate chooses which source elements participate. The Vn form reads those elements from the vector source. The VEA form first reads a complete vector-length source from memory and applies the same predicate selection.

Selected elements are compared as signed B, W, L, or Q values, and the least value becomes the reduction result. Its selected-width bit pattern occupies the low bits of Rn, and all higher bits are zero. If the predicate selects no elements, the result is the greatest signed value at the selected width.

2.75in

Encodings

VREDMINS.{B|W|L|Q}(z) Pn(p), Vn(v), Rn(r)

Format: Instruction format for VREDMINS.{B|W|L|Q}(z) Pn(p), Vn(v), Rn(r)

2.75in VREDMINS.{B|W|L|Q}(z) Pn(p), <ea>(e), Rn(r)

Format: Instruction format for VREDMINS.{B|W|L|Q}(z) Pn(p), <ea>(e), Rn(r)