Memory Model
The memory model defines instruction fetches, loads, stores, atomic read-modify-write operations, cache maintenance, and translation-cache maintenance after EA calculation and address translation.
Baseline Ordering
Normal memory is coherent. Every logical processor observes writes to a given byte in one common coherence order, and writes by one logical processor to that byte enter the order in program order. A naturally aligned tear-free scalar store enters that order as one memory write event.
Normal-memory writes are multi-copy atomic. When a memory write event becomes observable by a logical processor other than the writer, it becomes observable to all such logical processors at the same architectural point. An implementation may still forward a logical processor's own pending store to its later loads before that store is globally observable.
The baseline ordering is weak. Except for same-byte coherence or ordering imposed by an atomic memory-order selector or fence, loads and stores to different locations may be issued, completed, and observed in an order different from program order. Coherence and multi-copy atomicity do not by themselves order accesses to different locations.
Ordinary Load Values and Preserved Order
Each byte returned by a load comes from the initial value of that physical byte or from an actual store or successful atomic read-modify-write to that byte. A load does not obtain a value solely from a cyclic chain in which the load value is needed to produce the write that would supply it.
Among writes already globally observable when a load takes its value, the load observes the latest write in the byte's coherence order. A load may instead forward a byte from an earlier store by the same logical processor before that store is globally observable. A store later than the load in program order cannot supply the load.
Program order is preserved from an earlier read or write to a later write when their byte ranges overlap. Two loads of the same byte, with no intervening write by the same logical processor to that byte, do not observe the byte's coherence order moving backward. These rules apply independently to every byte of an access, including each visible portion of an unaligned access.
A load is ordered before a later memory access whose effective address depends on the loaded value. A load is also ordered before a later store when the stored value depends on the load or when execution of that store is control-dependent on the load. Control dependence alone does not order a later load; software uses an appropriate fence when that ordering is required.
PTE Cache Policies
The two-bit PTE.CP selects a cache policy for byte-addressed normal memory. Every policy uses the same coherence order, multi-copy atomicity, tearing rules, atomic operations, and fence semantics defined in this chapter. The policy changes allocation, retained cache state, and store combination; it does not create a separate value or ordering domain.
Normal-Memory Cache Policies
PTE.CP |
Policy | Reads and Fetches | Stores | Retained State |
|---|---|---|---|---|
0 |
Write-back cacheable | may allocate a coherent cache copy | may retire into a coherent dirty cache copy | clean or dirty coherent cache copies |
1 |
Coherent uncached | enter coherence without retaining a cache copy | enter coherence before retirement without retaining a dirty copy | no retained cache copy |
2 |
Coherent write-through | may allocate a coherent clean cache copy | enter coherence before retirement without retaining a dirty copy | clean coherent cache copies only |
3 |
Coherent write-combining | enter coherence without retaining a cache copy | may combine adjacent byte writes before entering coherence | pending combined stores, but no retained cache copy |
Aliases of one physical byte with different PTE.CP values participate in the same coherence order. A load, instruction fetch, or atomic operation through any alias observes the same physical value subject to ordinary ordering, and atomic operations serialize at the physical location. PTE.CP2 stores enter coherence before retirement and leave no dirty cache copy. PTE.CP3 combined stores preserve the byte writes and their per-location program order.
WFENCE and AFENCE complete earlier pending PTE.CP3 stores. WRBKDCACHE, FLSHDCACHE, and SYNCCACHE complete pending PTE.CP3 stores for their selected block before performing their named cache action. The data-write, cache-maintenance, rendezvous, and local instruction-cache sequence below applies without regard to the PTE.CP value used by the modified code mapping.
Access Atomicity and Alignment
Unaligned ordinary normal-memory accesses are architecturally permitted. A completed unaligned load may observe bytes from multiple memory events in coherence order, and a completed unaligned store may enter coherence as separately visible portions. Each visible store portion is coherent and multi-copy atomic.
An unaligned store is nevertheless fault-atomic for synchronous faults. If any byte of the complete store range would raise a synchronous fault, no byte of the store becomes architecturally visible.
Atomic read-modify-write instructions require natural byte alignment. A misaligned atomic operand raises ATOMIC_ALIGNMENT_FAULT before any memory update or architectural result commits; it must not complete as a non-atomic update.
For every scalar size, a naturally aligned normal-memory load or store is tear-free. Unaligned accesses retain the successful-access and synchronous-fault rules above.
Natural alignment equals the operand width in bytes: B is one byte and may use any byte address; W, L, and Q are two, four, and eight bytes and require addresses divisible by two, four, and eight respectively.
Stores to memory that is later executed as instructions are ordinary data stores until an explicit synchronization sequence makes the modified bytes visible to instruction fetch.
Cache-Maintenance Blocks
CPUID CACHE_TOPOLOGY reports a cache-maintenance granule \(G\). A cache-maintenance instruction computes and translates its address-role EA without reading an operand value, then selects the physical byte interval \([\lfloor A/G\rfloor G,\lfloor A/G\rfloor G+G)\) containing the translated physical address \(A\). One instruction operates on exactly that block. Because \(G\) is at most 4096 bytes, the selected physical block does not cross a 16 KiB page boundary.
FLSHDCACHE, INVDCACHE, and WRBKDCACHE apply to every data or unified cache copy of the selected block in its normal-memory coherence domain. FLSHDCACHE writes dirty bytes into normal-memory coherence and invalidates the copies. INVDCACHE discards the copies without writeback. WRBKDCACHE writes dirty bytes into normal-memory coherence and retains clean copies. Each operation completes the selected block before retirement.
INVICACHE invalidates the selected block in the executing logical processor's instruction cache, decoded instruction state, and instruction-prefetch state. SYNCCACHE first completes the data writeback for the block throughout the coherence domain, then performs the same local instruction-side invalidation, and finally serializes later instruction fetch so that it observes the synchronized bytes. To publish modified code to another logical processor, software completes SYNCCACHE on the publisher, performs a release/acquire rendezvous, and executes INVICACHE for the block on every receiving logical processor before branching to the modified bytes.
Address translation and permission checks precede a block's cache effects. A fault leaves that instruction's selected block unchanged.
Atomic Memory-Order Selectors
Atomic Memory-Order Selectors
| Selector | Code | Architectural Ordering Effect |
|---|---|---|
RELAXED |
0 |
Atomicity only. No ordering is imposed on unrelated memory operations. |
ACQUIRE |
1 |
Later memory operations by the same logical processor are ordered after the atomic operation. |
RELEASE |
2 |
Earlier memory operations by the same logical processor are ordered before the atomic operation. |
ACQREL |
3 |
Applies both acquire and release ordering. |
SEQCST |
4 |
Applies acquire-release ordering and participates in the single global sequentially consistent order. |
CMPXCHG, FETCHADD, FETCHSUB, FETCHAND, FETCHOR, and FETCHXOR are the atomic read-modify-write instructions. Each performs its memory read, successful memory write, and architectural register result as one indivisible operation in the coherence order of the addressed physical location.
A successful release or stronger atomic write heads a release sequence. The sequence continues through immediately following successful atomic read-modify-write operations to the same location in coherence order and ends before any other write. An acquire or stronger atomic operation that takes its value from any member of the sequence observes the effects ordered before its head before effects ordered after the acquiring operation.
One encoded selector governs the complete CMPXCHG operation on both success and failure. A failed CMPXCHG contributes a memory read event. Its acquire component orders later memory operations after that read, and its release component orders earlier memory operations before that read. On success, the memory write event carries the selected release effect to observers of that write; on failure, the read is the operation's memory event. A failed CMPXCHG contributes no write and therefore creates no release sequence. A failed CMPXCHG.SEQCST additionally participates in the global sequentially consistent order as an SC load.
Fence Instructions
The table gives every ordered-before pair imposed by a fence on memory operations issued by the same logical processor. An entry marked ordered places every earlier operation of the row kind before every later operation of the column kind.
Fence Ordered-Before Pairs
| Fence | read to read | read to write | write to read | write to write |
|---|---|---|---|---|
RFENCE |
ordered | baseline | baseline | baseline |
WFENCE |
baseline | baseline | baseline | ordered |
AFENCE |
ordered | ordered | ordered | ordered |
A baseline entry retains the weak-ordering rules of this chapter. AFENCE is cumulative: memory effects observed before the fence are propagated before effects ordered after it, including through another logical processor. The linked instruction entries define the matching completion behavior.
Global Sequentially Consistent Order
All AFENCE operations and all SEQCST atomic operations participate in one global total order that is consistent with each logical processor's ordered-before relation and with per-location coherence. A failed CMPXCHG.SEQCST participates in that order as an SC load even though it performs no write.
A naturally aligned tear-free scalar load or store also participates as an SC operation when it is the only memory access between its immediately surrounding AFENCE operations in memory-event order. Thus AFENCE; access; AFENCE is the architectural sequence for an SC scalar load or store. The access and both fences occupy their required positions in the same global order.
Acquire and release operations may be strengthened with AFENCE; the resulting instruction sequence has the union of the ordering constraints imposed by its operations. Leaf PTE.AM and PTE.CP are orthogonal. An MMIO access retains its non-speculative, operation-class, alignment, and ordering rules under every PTE.CP value. MMIO accesses from one logical processor are observed in program order relative to other MMIO accesses from that logical processor. Normal-memory and MMIO accesses retain the baseline weak ordering between classes; AFENCE orders earlier accesses before later accesses across that boundary.