ADC

Operation

Adds source and carry-in to the destination, writes the modular sum, and updates ZNCV.

Assembler Syntax

ADC.{B|W|L|Q}(z) Rn(s), Rn(d)

ADC.{B|W|L|Q}(z) Rn(s), <ea>(e)

ADC.{B|W|L|Q}(z) <ea>(e), Rn(s)

Privilege

Unprivileged

Repeat eligibility

REP eligible; REPcc observes dst

Adds the selected-width source value and the incoming FLAGS.C flag to the destination, writes the truncated sum, and updates FLAGS.Z, FLAGS.N, FLAGS.C, and FLAGS.V from the complete addition. The written destination result supplies the REPcc observed value.

Let \(n\) be the selected width, \(d\) and \(s\) the unsigned operand bit patterns, and \(c\) the incoming FLAGS.C. The written result is $\(r = (d + s + c) \bmod 2^n .\)$ FLAGS.Z is set when \(r=0\), and FLAGS.N receives the most-significant bit of \(r\). FLAGS.C reports an unsigned carry out of either addition. FLAGS.V reports signed overflow for the complete \(d+s+c\) operation.

2.75in

Encodings

ADC.{B|W|L|Q}(z) Rn(s), Rn(d)

Format: Instruction format for ADC.{B|W|L|Q}(z) Rn(s), Rn(d)

2.75in ADC.{B|W|L|Q}(z) Rn(s), <ea>(e)

Format: Instruction format for ADC.{B|W|L|Q}(z) Rn(s), <ea>(e)

dst — excluded: immediate [invalid_destination]

2.75in ADC.{B|W|L|Q}(z) <ea>(e), Rn(s)

Format: Instruction format for ADC.{B|W|L|Q}(z) <ea>(e), Rn(s)