VMINS

Operation

Selects the lesser signed value from each active destination/source element pair.

Assembler Syntax

VMINS.{B|W|L|Q}(z) Pn(p), Vn(v), Vn(w)

VMINS.{B|W|L|Q}(z) Pn(p), <ea>(e), Vn(v)

VMINS.{B|W|L|Q}(z) Pn(p), Vn(v), <ea>(e)

Privilege

Unprivileged

Required CPUID flags

VECTOR

The governing predicate selects destination elements for update. For each selected element, the old destination and corresponding source are interpreted as two's-complement signed B, W, L, or Q values. The lesser value's bit pattern replaces the destination element. An unselected destination element retains its previous bit pattern.

The register form reads both operands from corresponding vector lanes. The memory-source form reads the source elements from memory and updates destination register lanes. The memory-destination form reads each selected destination element, compares it with the corresponding source-register lane, and writes the selected bit pattern back to that memory element.

2.75in

Encodings

VMINS.{B|W|L|Q}(z) Pn(p), Vn(v), Vn(w)

Format: Instruction format for VMINS.{B|W|L|Q}(z) Pn(p), Vn(v), Vn(w)

2.75in VMINS.{B|W|L|Q}(z) Pn(p), <ea>(e), Vn(v)

Format: Instruction format for VMINS.{B|W|L|Q}(z) Pn(p), <ea>(e), Vn(v)

2.75in VMINS.{B|W|L|Q}(z) Pn(p), Vn(v), <ea>(e)

Format: Instruction format for VMINS.{B|W|L|Q}(z) Pn(p), Vn(v), <ea>(e)

dst — excluded: immediate [invalid_destination]