VCLS

Operation

Counts consecutive one bits from the high end of each active element.

Assembler Syntax

VCLS.{B|W|L|Q}(z) Pn(p), Vn(v)

VCLS.{B|W|L|Q}(z) Pn(p), <ea>(e), Vn(v)

VCLS.{B|W|L|Q}(z) Pn(p), Vn(v), <ea>(e)

Privilege

Unprivileged

Required CPUID flags

VECTOR

The register form replaces each active destination lane with the count of consecutive one bits at the high end of its old selected-width value. The memory-source form counts leading one bits in each active memory element and writes the result to the corresponding destination lane. An inactive destination lane retains its previous value.

The memory-destination form counts leading one bits in each active source-register lane and writes the result to the corresponding memory element. An inactive memory element remains unchanged. If every bit in an element is one, the result equals the element width in bits.

2.75in

Encodings

VCLS.{B|W|L|Q}(z) Pn(p), Vn(v)

Format: Instruction format for VCLS.{B|W|L|Q}(z) Pn(p), Vn(v)

2.75in VCLS.{B|W|L|Q}(z) Pn(p), <ea>(e), Vn(v)

Format: Instruction format for VCLS.{B|W|L|Q}(z) Pn(p), <ea>(e), Vn(v)

2.75in VCLS.{B|W|L|Q}(z) Pn(p), Vn(v), <ea>(e)

Format: Instruction format for VCLS.{B|W|L|Q}(z) Pn(p), Vn(v), <ea>(e)

dst — excluded: immediate [invalid_destination]