VFCVTS

Operation

Converts active half-precision, double-precision, or signed integer elements to single precision.

Assembler Syntax

VFCVTS.{H|D}(z) Pn(p), Vn(v), Vn(w)

VFCVTS.{L|Q}(z) Pn(p), Vn(v), Vn(w)

Privilege

Unprivileged

Required CPUID flags

FP

VECTOR

VECTORFP

Each active H or D source value is converted to S. The signed-integer forms convert each active L or Q source value to S. The operation container is the larger of the source and 32-bit destination widths. The S result replaces the low 32-bit field; the other bits of an active destination container and every inactive container retain their previous values.

A completed conversion accrues generated NV, OF, UF, and NX causes in FFLAGS; DZ is unchanged. An enabled generated cause raises FLOATING_POINT_EXCEPTION and suppresses destination and newly accrued FFLAGS effects.

Each 64-bit operation container reads one double-precision source. The active container writes a single-precision result into its low field and retains the upper destination field; the inactive container remains unchanged.

VFCVTS.D double-to-single conversion containers

2.75in

Encodings

VFCVTS.{H|D}(z) Pn(p), Vn(v), Vn(w)

Format: Instruction format for VFCVTS.{H|D}(z) Pn(p), Vn(v), Vn(w)

Format: Instruction format for VFCVTS.{H|D}(z) Pn(p), Vn(v), Vn(w)

size — allowed: 1, 3 [reserved_vector_element_type]

2.75in VFCVTS.{L|Q}(z) Pn(p), Vn(v), Vn(w)

Format: Instruction format for VFCVTS.{L|Q}(z) Pn(p), Vn(v), Vn(w)

Format: Instruction format for VFCVTS.{L|Q}(z) Pn(p), Vn(v), Vn(w)

size — allowed: 0x2..0x3 [reserved_vector_element_type]