VCMPcc

Operation

Compares active integer lanes and writes a complete predicate image.

Assembler Syntax

VCMPcc.{B|W|L|Q}(x) Pn(p), Vn(v), Vn(w), Pn(q)

VCMPcc.{B|W|L|Q}(x) Pn(p), Vn(v), <ea>(e), Pn(q)

Privilege

Unprivileged

Required CPUID flags

VECTOR

VCMPcc compares corresponding active elements under the encoded condition. The register form reads both elements from vector registers. The memory form reads the right-hand element from the corresponding active VEA location.

B, W, L, and Q forms apply the selected integer condition.

The destination is a complete predicate image. A significant result bit is set when its governing bit is set and the selected relation is true. Every other predicate bit is clear.

2.75in

Encodings

VCMPcc.{B|W|L|Q}(x) Pn(p), Vn(v), Vn(w), Pn(q)

Format: Instruction format for VCMPcc.{B|W|L|Q}(x) Pn(p), Vn(v), Vn(w), Pn(q)

size — allowed: 0x0..0x3 [reserved_vector_element_type]

cc — allowed: 0x2..0x5, 0xa..0xf [reserved_vector_comparison_condition]

2.75in VCMPcc.{B|W|L|Q}(x) Pn(p), Vn(v), <ea>(e), Pn(q)

Format: Instruction format for VCMPcc.{B|W|L|Q}(x) Pn(p), Vn(v), <ea>(e), Pn(q)

size — allowed: 0x0..0x3 [reserved_vector_element_type]

cc — allowed: 0x2..0x5, 0xa..0xf [reserved_vector_comparison_condition]