Scalable-Vector Instructions
Summary
Scalable-Vector Instructions Summary (Informative)
| Mnemonic | Brief description |
|---|---|
| Restores the vector user-state record. | |
| Saves the vector user-state record. | |
| Broadcasts an integer scalar register or immediate value to every vector lane. | |
| Copies or merges vector elements between registers and contiguous memory. | |
| Sets predicate positions from the count remainder through the final lane. | |
| Set significant positions before unsigned(Rcount) mod lane_count. | |
| Return the first selected element index at a significant position. | |
| Return the last selected element index at a significant position. | |
| Count set significant positions for the selected element size. | |
| AND corresponding bits of Ps and the old Pd into the complete Pd image. | |
| OR corresponding bits of Ps and the old Pd into the complete Pd image. | |
| XOR corresponding bits of Ps and the old Pd into the complete Pd image. | |
| Unpacks the lower half of source predicate positions into wider destination positions. | |
| Unpacks the upper half of source predicate positions into wider destination positions. | |
| Packs source predicate positions into the lower half of narrower destination positions. | |
| Packs source predicate positions into the upper half of narrower destination positions. | |
| Writes zero to every byte of the complete destination vector image. | |
| Writes each logical lane number to its destination element. | |
| Write the number of lanes of the selected element width. | |
| Add a signed immediate multiple of the selected lane count to Rn. | |
| Gather governed vector lanes while journaling completed lanes in a predicate. | |
| Scatter governed vector lanes while journaling completed lanes in a predicate. | |
| Set every significant position for the selected size. | |
| Clear the complete predicate image. | |
| Complements every bit of the complete Pd image. | |
| Branch if any bit is set. | |
| Branch if no bit is set. | |
| Branch if every significant position for the selected size is set. | |
| Negates active integer elements. | |
| Computes the absolute value of active integer elements. | |
| Complements every bit of each active element. | |
| Counts consecutive zero bits from the high end of each active element. | |
| Counts consecutive zero bits from the low end of each active element. | |
| Counts consecutive one bits from the high end of each active element. | |
| Counts consecutive one bits from the low end of each active element. | |
| Counts the set bits in each active element. | |
| Reverses the byte order within each active element. | |
| Select predicate lanes using unsigned vector indices. | |
| Move predicate lanes toward higher indices and insert zero at the low end. | |
| Move predicate lanes toward lower indices and insert zero at the high end. | |
| Compares active integer lanes and writes a complete predicate image. | |
| Sets significant result bits where the governed element-wise AND is zero and clears all other bits. | |
| Sets significant result bits where the governed element-wise AND is nonzero and clears all other bits. | |
| Adds corresponding active integer vector elements. | |
| Subtracts corresponding active integer vector elements. | |
| Multiplies corresponding active integer elements. | |
| Applies bitwise AND to corresponding active vector elements. | |
| Applies bitwise OR to corresponding active vector elements. | |
| Applies bitwise XOR to corresponding active vector elements. | |
| Selects the lesser signed value from each active destination/source element pair. | |
| Selects the lesser unsigned value from each active destination/source element pair. | |
| Selects the greater signed value from each active destination/source element pair. | |
| Selects the greater unsigned value from each active destination/source element pair. | |
| Writes the high half of each active signed destination/source product. | |
| Writes the high half of each active unsigned destination/source product. | |
| Writes the high half of each active signed-destination by unsigned-source product. | |
| Logically shifts each active integer element left by its selected-width count. | |
| Logically shifts each active integer element right by its selected-width count. | |
| Arithmetically shifts each active integer element right by its selected-width count. | |
| Rotates each active integer element left by its selected-width count. | |
| Rotates each active integer element right by its selected-width count. | |
| Zero-extends B source elements to W destination elements. | |
| Sign-extends B source elements to W destination elements. | |
| Zero-extends B or W source elements to L destination elements. | |
| Sign-extends B or W source elements to L destination elements. | |
| Zero-extends B, W, or L source elements to Q destination elements. | |
| Sign-extends B, W, or L source elements to Q destination elements. | |
| Copies the low B field from each W, L, or Q source container. | |
| Copies the low W field from each L or Q source container. | |
| Copies the low L field from each Q source container. | |
| Select source lanes with vector indices; out-of-range indices produce zero. | |
| Interleave the lower halves of the old destination and source. | |
| Interleave the upper halves of the old destination and source. | |
| Gather even lanes from the old destination and source into separate result halves. | |
| Gather odd lanes from the old destination and source into separate result halves. | |
| Interleave even lanes from the old destination and source by adjacent result pairs. | |
| Interleave odd lanes from the old destination and source by adjacent result pairs. | |
| Extract a lane window from the old destination followed by a source vector. | |
| Move old destination lanes toward higher indices and zero vacated lanes. | |
| Move old destination lanes toward lower indices and zero vacated lanes. | |
| Copies one indexed integer vector lane to an integer scalar register. | |
| Replaces one indexed vector lane with an integer scalar value. | |
| Reduces active integer elements to one scalar sum. | |
| Finds the signed minimum of selected integer lanes and writes the scalar result to Rn. | |
| Finds the unsigned minimum of selected integer lanes and writes the scalar result to Rn. | |
| Finds the signed maximum of selected integer lanes and writes the scalar result to Rn. | |
| Finds the unsigned maximum of selected integer lanes and writes the scalar result to Rn. | |
| Reduces selected integer lanes with bitwise AND and writes the scalar result to Rn. | |
| Reduces selected integer lanes with bitwise OR and writes the scalar result to Rn. | |
| Reduces selected integer lanes with bitwise XOR and writes the scalar result to Rn. | |
| Replace bits of Pd selected by Pc with bits from Ps. | |
| Interleave the lower halves of two predicate-lane sequences. | |
| Interleave the upper halves of two predicate-lane sequences. | |
| Concatenate even-position predicate lanes from two sources. | |
| Concatenate odd-position predicate lanes from two sources. | |
| Interleave even-position predicate lanes from two sources. | |
| Interleave odd-position predicate lanes from two sources. | |
| Extract a predicate-lane window from the old destination followed by a source predicate. | |
| Loads active memory elements and clears inactive destination lanes. | |
| Builds the next predicate chunk from a remaining count and lane offset. | |
| Transfers a complete packed predicate image between a predicate register and memory. |
Element Types and Assembly Spelling
A size-bearing VECTOR instruction has one suffix. The integer element suffixes B, W, L, and Q select 1-, 2-, 4-, and 8-byte elements.
The three-bit tzz selector values zero through three select B/W/L/Q; value four is invalid. The two-bit zz selector in integer families assigns all four values to B/W/L/Q. A reserved selector does not name another data format.
The suffix is the source width for a width-changing instruction; the destination width and signedness are part of the mnemonic. For example, VEXTZQ.B zero-extends a byte into a quadword. Predicate operations, VLCNT, VLCADD, VGATHER, VSCATTER, PLOOP, VMOV, VMOVZ, and the permute, slide, slice, and zip families use B/W/L/Q; H/S/D width-only aliases are not defined.
Predicates and Destination Images
For an element size of \(E\) bytes, logical lane \(i\) is governed by predicate bit \(iE\). All other predicate bits are outside the typed predicate image for that operation. Unless an instruction explicitly produces a complete predicate image or uses zeroing movement, a false governing bit annuls that lane: it performs no memory access, produces no exception, and preserves the old destination lane.
An instruction that writes a predicate result writes a complete packed predicate image. It sets or clears each significant result bit and clears all bits outside the typed predicate image. Integer comparisons support EQ, NE, ULT, UGE, ULE, UGT, LT, GE, LE, and GT. VECTORFP defines its own floating-point comparison forms. VTESTZ and VTESTNZ are distinct integer test operations. Vector integer operations do not update scalar FLAGS.
Integer reductions return a zero-extended result in an Rn. For an empty predicate, ADD, OR, and XOR return zero; AND and unsigned MIN return the all-ones value of the selected width; signed MIN returns the signed maximum; signed MAX returns the signed minimum; and unsigned MAX returns zero.
PLOOP consumes a remaining-count register and an offset register. If the remaining count is zero, it takes its encoded branch target and does not change the predicate or either register. Otherwise, an offset greater than or equal to the selected lane count raises VECTOR_LANE_INDEX_OUT_OF_RANGE with error code zero and leaves the instruction uncommitted. A valid nonzero iteration activates the next \(\min(remaining, lane\_count-offset)\) lanes, subtracts that number from the remaining count, clears the offset register, and falls through. Software advances the offset between chunks when it needs a nonzero subsequent chunk origin.
Lane Mapping and Scalar Bridges
Vector bytes use increasing-address little-endian order. A same-width operation treats a vector as VLEN divided by the selected element width lanes. For widening and narrowing, the operation container is the larger of the source and destination widths. Each active container reads the source value from its low source-width part and writes the result into its low destination-width part. Other bits of an active destination container and every inactive container remain unchanged.
VDUP broadcasts a scalar register or immediate into every lane. VEXTRACT and VINSERT use a scalar lane index. An index at or above the lane count raises VECTOR_LANE_INDEX_OUT_OF_RANGE with error code one and commits no state. VLCNT returns VLEN in bytes divided by the selected element width in bytes. VLCADD adds its signed eight-bit immediate multiplied by that lane count to its scalar destination modulo \(2^{64}\). These operations preserve FLAGS and use the integer B/W/L/Q suffixes. VECTORFP provides the corresponding floating-point scalar bridges.
Vector Memory Operations
A vector memory operand uses the ordinary compact, EXT1, and EXT2 descriptor formats in vector context. The descriptor computes one scalar anchor address. A contiguous access uses
All arithmetic is modulo \(2^{64}\). Existing effective-address auto-update is applied once to the scalar anchor in the ordinary architectural order. That single update covers all lanes.
Inactive lanes issue no memory transaction. VMOV merges a memory source into its destination, while VMOVZ writes zero to inactive destination lanes. A memory-destination arithmetic form uses non-atomic, lane-wise read-modify-write semantics. A vector instruction nevertheless has one architectural commit point: address evaluation, all active reads, computation, and all active writes must succeed before any register, predicate, memory, auto-update, FFLAGS, or PC effect becomes visible. After range, wrap, and canonicality checks, the implementation completes translation of every mapping covered by every active lane in increasing linear-address order. Only after all such translations succeed does it apply physical-class checks, the vector/gather/scatter MMIO-operation prohibition, alignment checks, and target or bus accesses, in that order. Consequently, a translation fault in a higher-address active lane takes precedence over an MMIO condition discovered in a lower-address active lane. When logical lane order differs from address order, translation and translation-fault selection still follow address order. The reported fault address identifies the lane whose range supplies the selected failure.
Resumable Gather and Scatter
VGATHER and VSCATTER are full-vector memory instructions with an explicit completion predicate. Their canonical operand orders are illustrated below; \(T\) denotes the selected B/W/L/Q element width.
VGATHER.T Pg, Ps, [address], Vd
VSCATTER.T Pg, Ps, Vs, [address]
Typed completion image.
For element width \(E\) bytes, let \(N=VLEN/(8E)\). Define \(G=typed_E(Pg)\) by copying Pg[iE] to bit \(iE\) for every \(0\leq i<N\) and clearing every other predicate bit. At each entry or re-entry, the instruction performs the architectural normalization
Pg and Ps shall be distinct. The normalization is committed before a lane memory transaction is issued and remains visible if that transaction faults. Consequently inactive completion bits and all bits outside the typed predicate image are zero. If pending is empty, the instruction retires without a memory transaction and its normal postcondition is Ps == G.
Otherwise the implementation selects any pending lane \(i\). VGATHER performs one \(E\)-byte load and, on success, writes only Vd[i] before setting Ps[iE]. VSCATTER performs one \(E\)-byte store of Vs[i] and, on success, sets Ps[iE]. Every successful lane therefore has one completion bit that journals its externally visible work. VGATHER requires its vector address register to differ from Vd; VSCATTER permits its vector address register and Vs to be the same register.
Lane-completion boundary.
After a successful lane, destination or memory state and the corresponding completion bit commit together. If another lane is pending, the PC remains at the gather or scatter instruction and an asynchronous event may be admitted. This progress boundary is not architectural instruction retirement, does not increment an architectural retired-instruction count, and does not itself generate a debug-trace event. The final empty-pending transition advances the PC and forms the ordinary retirement and trace boundary.
An event handler may emulate or waive a faulting lane by setting its completion bit. For VGATHER, emulation shall first write the lane’s destination value; for VSCATTER, it shall first perform or explicitly waive the store. Returning to the saved PC is sufficient to continue: no hidden cursor or implementation token is part of architectural state.
Address forms.
The lane number \(i\) is implicit and does not appear in assembly syntax. Before default-data-segment translation, the address forms are:
| Canonical address | Constraint | Lane offset |
|---|---|---|
[Rb + Rs] |
any \(T\) | \(Rb+i\mathbin{\cdot}signed64(Rs)\) |
[Va] |
L |
\(zero\_extend_{64}(Va.L[i])\) |
[Va] |
Q |
\(Va.Q[i]\) |
[Rb + Va] |
any \(T\) | \(Rb+sign\_extend_{64}(Va.T[i])\) |
[Rb + Va * scale] |
any \(T\) | \(Rb+zero\_extend_{64}(Va.T[i])E\) |
[Rb + Va * scale + disp] |
any \(T\) | preceding indexed address plus disp |
In the scalar-stride form, Rs supplies the signed lane stride even though the canonical spelling is the familiar-looking [Rb + Rs]. In vector-index forms, the assembler token scale is fixed by \(T\) to \(E\); it is not an additional operand. The disp8s, disp16s, and disp32s payloads are sign-extended, while disp64 contributes its exact 64-bit bit pattern. All address arithmetic is modulo \(2^{64}\). The absolute forms are still offsets through the default data segment and do not bypass segmentation.
Ordering, overlap, and failures.
Lane selection and memory-access order are not architecturally specified. Each successful lane access is nevertheless one ordinary, naturally sized \(E\)-byte normal-memory access and obeys the baseline memory-ordering rules. If two VSCATTER lanes target overlapping physical bytes, which lane supplies the final value of each overlapping byte is unspecified. This does not merge, drop, or widen either access: each successful lane still performs its own \(E\)-byte store and sets its own completion bit.
A load fault or a scatter failure reported before the store point of no return leaves the selected lane pending and raises the ordinary precise synchronous fault. An ordinary memory bus failure in this state is retry-safe. If a scatter store has become irrevocable, the implementation sets the lane’s completion bit and shall not report a restartable synchronous failure for that lane. Any later report is an imprecise MACHINE_CHECK delivered at a subsequent lane or retirement boundary after the store becomes irrevocable. These instructions are not permitted for MMIO, including when only one lane is active. Both preserve FLAGS.
Execution and Saved State
The vector user-state record contains the complete scalable vector and packed predicate images selected by its presence bitmap. A committed Vn or Pn write marks vector state modified. Architectural event entry does not otherwise change vector state.
An implementation may internally coalesce eligible scalar REP or REPcc iterations into vector-sized work. This permission creates no vector instruction, predicate, or additional repeat state. The observable counter, condition, FLAGS, memory, auto-update, fault, event, and restart behavior must equal the scalar iteration sequence, and only the scalar prefix preceding the first fault or terminating REPcc observation may commit.