VFREDADD

Operation

Reduces active floating-point elements to one scalar sum.

Assembler Syntax

VFREDADD.{H|S|D}(z) Pn(p), Vn(v), Fn(r)

VFREDADD.{H|S|D}(z) Pn(p), <ea>(e), Fn(r)

Privilege

Unprivileged

Required CPUID flags

FP

VECTOR

VECTORFP

The governing predicate selects the source elements from Vn or the corresponding contiguous memory locations. The H, S, and D forms begin with positive zero and add active elements in increasing logical-lane order without reassociation. An empty floating-point selection therefore produces positive zero. A completed floating-point reduction accrues generated NV, OF, UF, and NX causes in FFLAGS; DZ is unchanged. An enabled generated cause raises FLOATING_POINT_EXCEPTION and suppresses the scalar result and newly accrued causes.

The active single-precision values f0, f2, and f3 are added after positive zero in increasing logical-lane order, and the fold result is written to Fn.

VFREDADD.S ordered floating-point reduction

2.75in

Encodings

VFREDADD.{H|S|D}(z) Pn(p), Vn(v), Fn(r)

Format: Instruction format for VFREDADD.{H|S|D}(z) Pn(p), Vn(v), Fn(r)

Format: Instruction format for VFREDADD.{H|S|D}(z) Pn(p), Vn(v), Fn(r)

size — allowed: 0x1..0x3 [reserved_vector_element_type]

2.75in VFREDADD.{H|S|D}(z) Pn(p), <ea>(e), Fn(r)

Format: Instruction format for VFREDADD.{H|S|D}(z) Pn(p), <ea>(e), Fn(r)

Format: Instruction format for VFREDADD.{H|S|D}(z) Pn(p), <ea>(e), Fn(r)

size — allowed: 0x1..0x3 [reserved_vector_element_type]