Instruction Execution Model
This section defines the common execution rules used by the instruction descriptions. An individual instruction may add stricter rules, but it does not silently replace the rules below.
Architectural Result Priority
When one instruction could encounter more than one exceptional condition, the architecturally reported result is the first applicable condition in the following order.
-
Instruction fetch and fetch translation.
-
Instruction framing and acquisition of the complete instruction record.
-
Opcode recognition.
-
Availability of every extension required by the decoded operation.
-
Fixed-field, reserved-field, and effective-address-form legality.
-
Privilege checks.
-
Selector, control-image, and other architectural-state validation.
-
Predicate evaluation for a conditional operation.
-
Every enabled operand access in architectural access order.
-
Execution-stage faults defined by the decoded operation.
A false predicate suppresses the conditional operation's target-memory and implicit stack accesses. It does not suppress instruction framing, opcode and extension checks, encoding legality, privilege checks, or control-state validation. Explicit operands are accessed in instruction operand order unless an instruction states another order. For a memory-to-memory operation, the complete source read precedes access to the destination, so a source-access failure has priority over a destination-access failure.
Implicit accesses use the order stated by the instruction. In particular, PUSH captures its source before accessing the destination stack slot; POP reads the stack slot before validating or writing its destination; PUSHP uses listed register order and POPP uses reverse listed order; CALL validates its target before accessing the return stack; RET reads the return stack before validating its target; and Long Call, Long Return, Event Return, and supervisor-entry instructions use the step order in their instruction descriptions.
Implicit Stack Operations
Ordinary implicit stack operations capture the current SS and SP before their first stack access. Every stack slot is 64 bits and is addressed through the captured SS. The ranges below are expressed in terms of the captured \(SP_{\mathrm{old}}\); the applicable segment, translation, and complete-range checks finish before the operation commits.
Ordinary Implicit Stack Operations
| Operation | Stack range | Committed SP | Slot layout or value order |
|---|---|---|---|
PUSH, CALL |
\([SP_{\mathrm{old}}-8,SP_{\mathrm{old}})\) | \(SP_{\mathrm{old}}-8\) | one source value or the following instruction's continuation PC at \(SP_{\mathrm{old}}-8\) |
POP, RET |
\([SP_{\mathrm{old}},SP_{\mathrm{old}}+8)\) | \(SP_{\mathrm{old}}+8\) | one destination value or continuation PC read at \(SP_{\mathrm{old}}\) |
PUSHP |
\([SP_{\mathrm{old}}-16,SP_{\mathrm{old}})\) | \(SP_{\mathrm{old}}-16\) | listed pair's second register at \(SP_{\mathrm{old}}-16\) and first register at \(SP_{\mathrm{old}}-8\) |
POPP |
\([SP_{\mathrm{old}},SP_{\mathrm{old}}+16)\) | \(SP_{\mathrm{old}}+16\) | listed pair's second register from \(SP_{\mathrm{old}}\), then first register from \(SP_{\mathrm{old}}+8\) |
LCALL |
\([SP_{\mathrm{old}}-16,SP_{\mathrm{old}})\) | \(SP_{\mathrm{old}}-16\) | continuation PC at \(SP_{\mathrm{old}}-16\) and return CS image at \(SP_{\mathrm{old}}-8\) |
LRET |
\([SP_{\mathrm{old}},SP_{\mathrm{old}}+16)\) | \(SP_{\mathrm{old}}+16\) | continuation PC at \(SP_{\mathrm{old}}\) and return CS image at \(SP_{\mathrm{old}}+8\) |
The complete range and all source values are established before a push operation changes memory or SP. A pop operation reads its complete range and completes any applicable destination validation before changing a destination or SP. A successful operation commits all listed stack and register effects together; a preceding fault exposes none of them.
Architectural event entry and ERET use the return source selected by the Architectural Event Processing Model. SYSCALL is the SYSTEM_CALL event; user-origin entry keeps its continuation in the user context bank described by the Privileged Execution Model and creates no memory frame.
Floating-Point Implicit Stack Operations
FPUSHP and FPOPP follow the base implicit-stack rules for register-pair operations. FPUSHP writes the listed pair's second register at \(SP_{\mathrm{old}}-16\) and first register at \(SP_{\mathrm{old}}-8\), then commits \(SP_{\mathrm{old}}-16\). FPOPP reads the listed pair's second register at \(SP_{\mathrm{old}}\) and first register at \(SP_{\mathrm{old}}+8\), then commits \(SP_{\mathrm{old}}+16\). Both operations establish the complete 16-byte range and all values before committing any register or SP effect.
Operand Evaluation and EA Defaults
Operands are decoded in instruction order. Source reads complete before the final destination write unless an atomic instruction says otherwise. Effective-address calculation may produce an address without reading memory.
Auto-update EA forms update temporary operand-evaluation state. The architectural register update becomes visible only when the instruction commits.
Ordinary instructions accept at most one memory operand. The explicitly encoded memory-memory exceptions are CMP, EXTSL, EXTSQ, EXTSW, EXTZL, EXTZQ, EXTZW, MOV, MOVCU, MOVUC, MOVUU, FBNDII, FBNDIX, FBNDXI, FBNDXX. Repeat behavior is available only through the repeat instructions and body-eligibility rules defined in Repeated Scalar Execution.
An instruction either replaces the complete FLAGS.Z, FLAGS.N, FLAGS.C, and FLAGS.V FLAGS image or preserves the complete image; partial FLAGS writes do not exist. Operand evaluation follows instruction operand order, and an instruction has one architectural commit point unless its description explicitly defines partial completion.
Shared Side-Effect Rules
An instruction that faults before commit leaves destination registers, destination memory, and auto-update register effects unchanged unless the instruction explicitly defines partial completion.
Atomic read-modify-write instructions have a single architectural commit point for the memory update and any associated register result. Cache, TLB, and system-state instructions describe their own completion and visibility rules.
Ordinary integer ALU instructions use the common one-memory-operand rule. Compare and test instructions may read two operands and update FLAGS without storing their temporary result. EXTS and EXTZ additionally provide explicitly encoded register-memory and memory-memory conversion stores; EXTSQ also provides register-register and memory-register sign extension. These operations preserve FLAGS unless a repeat rule observes a derived value. Data movement, LEA, and segment-address operations also preserve FLAGS unless their descriptions say otherwise.
Control transfers make PC and CS changes at a single control-transfer commit point. Atomic operations require a naturally aligned addressable memory operand and commit the read-modify-write as one architectural update. TLB, page-table context, and privileged control operations require supervisor privilege. Cache-maintenance operations preserve FLAGS and define their own visibility rules.