FPUSHP

Operation

Pushes one canonical floating-point register pair selected by an inline pair index.

Assembler Syntax

FPUSHP FPAIRn(i)

Privilege

Unprivileged

Required CPUID flags

FP

Repeat eligibility

REP eligible

Pushes the canonical floating-point register pair selected by the pair ID. The canonical pair sequence is pair 0 (F0, F1), pair 1 (F2, F3), pair 2 (F4, F5), pair 3 (F6, F7), pair 4 (F8, F9), pair 5 (F10, F11), pair 6 (F12, F13), and pair 7 (F14, F15). All eight pair IDs are valid and each selects one pair.

FPUSHP selects one canonical floating-point pair using the unsigned 3-bit pair index and processes that pair's registers in the listed order. The complete two-slot stack range is validated before either slot or SP is changed. Each register push decrements SP by 8 and then stores the 64-bit floating-point register value at the new SP.

2.75in

Encodings

FPUSHP FPAIRn(i)

Format: Instruction format for FPUSHP FPAIRn(i)