Reading an Instruction Description

Entry Organization

Each instruction entry presents its Operation and Assembler Syntax before applicability, repeat, event, and status information relevant to that instruction. Detailed Semantics supplies the conditions and effects needed to complete the Operation. Illustrative diagrams follow that explanation and precede the concrete encodings. Each mnemonic begins on a new page so its encoding diagrams, field explanations, and side-effect text stay together as one reference unit.

Assembler Source Grammar

The assembler source language is a sequence of newline-terminated statements. Whitespace may separate tokens except where an instruction spelling joins a mnemonic, size or condition suffix, or modifier. A label may precede a statement on the same line, and a line may contain labels without an instruction or directive.

source              ::= { line }
line                ::= { label ":" } [ statement ] end-of-line
statement           ::= instruction | directive
instruction         ::= instruction-form [ ":" "LEN" integer
                        [ "," padding-byte-list ] ]
instruction-form    ::= mnemonic-form [ operand-list ]
operand-list        ::= operand { "," operand }
padding-byte-list   ::= padding-byte { "," padding-byte }
padding-byte        ::= integer | "ILLEGAL" | "NOP"
operand             ::= register-name
                      | expression
                      | address-expression
                      | register-mask
                      | "(" instruction ")"
address-expression  ::= "[" ea-expression "]"
symbol-reference    ::= bare-identifier | quoted-identifier
quoted-identifier   ::= "`" { quoted-character | escape } "`"
escape              ::= "\`" | "\\"

This grammar is an envelope, not a second declaration of the instruction set. The instruction encoding catalog is the sole definition of the accepted mnemonic forms, suffixes, modifiers, operand counts, operand ordering, and operand classes. A parenthesized instruction is accepted only where an instruction form declares an instruction operand. The effective-address mode catalog is the sole definition of the accepted ea-expression forms. The brackets delimit address expressions only and never enclose another operand class. Whether a consuming instruction reads memory, writes memory, computes the address only, or applies another address-directed operation is defined by that instruction's operand role.

The optional : LEN n annotation requests an encoded extended instruction length of n bytes. If no padding-byte list follows, the assembler fills every trailing padding byte with ILLEGAL, whose canonical one-byte encoding is zero. If a list is present, each item specifies one trailing padding byte in instruction-stream order; its item count must equal the requested length minus the required instruction length. NOP denotes its canonical one-byte encoding, and an integer padding byte must be an absolute value from 0 through 255. Padding bytes do not accept expressions or relocations.

Register names are recognized case-insensitively. Symbol names are case-sensitive. A bare identifier that is a register name denotes that register in a context that accepts it; every other bare identifier in an expression denotes a symbol. Backtick quoting may be applied to any symbol reference and forces the enclosed name to be interpreted as a symbol, so R1 denotes the register while ‘R1‘ denotes the distinct symbol named R1. Within a quoted identifier, \ denotes a literal backtick and \\ denotes a literal backslash. No other escape is defined, and a quoted identifier cannot cross a newline.

A relocation annotation follows the complete symbol reference and is not part of the quoted name. For example, ‘R1‘@abs64 applies abs64 to the symbol R1, whereas ‘R1@abs64‘ names a symbol whose name contains the characters @abs64. An assembler emits an unquoted symbol when its name is a valid bare identifier that does not collide with a register name; otherwise it emits the canonical backtick-quoted form.

Mnemonics and Suffixes

The B, W, L, and Q suffixes select 8-, 16-, 32-, and 64-bit integer sizes.

When an instruction encoding includes a size selector z, its definition maps z to the suffix set shown for that encoding. A mnemonic without a size suffix has a single architecturally defined size or no data-size operand. Conditional mnemonic variants use the condition names listed in the Flags and Condition Codes chapter.

CMPJcc, DJcc, IJcc, Jcc, MOVcc, SETcc, and TESTJcc place the condition suffix in the mnemonic. An encoding with only one architectural size omits the size suffix.

Operand and Status Notation

Rn names an Rn register selected from the general-purpose registers R0 through R15; SP and PC are special registers outside that encoding namespace. An <ea> operand names a compact effective-address field and any appended EA payload.

FLAGS and STATUS are architectural state registers. Instruction descriptions state whether an encoding updates, preserves, reads, or ignores each status register. A FLAGS update always names and replaces the complete ZNCV image.

In a transposed flag-effects table, - marks an unchanged flag and 0 or 1 marks a constant result. * marks the single table-defined effect described by that table's local legend. When a table contains multiple table-defined effects, letters a through z distinguish their local legend entries.

In instruction pseudocode, Operand Read applies the addressing mode and operation size. Operand Write stores the selected-size result; an Rn write defines all 64 bits and extends a sub-Q result according to the common integer result-extension rule, while a memory write changes only the selected bytes. EA Address computes an address without reading memory. A control-target memory operand reads its declared-width target, while a control-target register or immediate operand supplies the target value directly. A selector may name an Rn register, a segment register, or an encoded immediate. FLAGS ZNCV refers to the integer FLAGS.Z, FLAGS.N, FLAGS.C, and FLAGS.V bits.

Encodings

In an encoding diagram, fixed 0 and 1 fields identify framing, opcode-selection, or reserved values, and the notes below decode lettered fields. An \<ea> field is the compact effective-address field and may select one or more independently determined EA payloads in operand order.

In each instruction entry, Encodings presents the encoding variants, operand and effective-address grammar, and size selectors.

For an extended encoding, the four-bit L field selects a 3+L-byte encoded instruction length. The required instruction length is the opcode-space length plus the selected operand payload lengths. Every larger encoded instruction length through 18 bytes is valid, and the trailing bytes are uninterpreted padding. The LEN n, spelling records an explicit encoded instruction length.