VFCVTD

Operation

Converts active half-precision, single-precision, or signed integer elements to double precision.

Assembler Syntax

VFCVTD.{H|S}(z) Pn(p), Vn(v), Vn(w)

VFCVTD.{L|Q}(z) Pn(p), Vn(v), Vn(w)

Privilege

Unprivileged

Required CPUID flags

FP

VECTOR

VECTORFP

Each active H or S source value is converted to D. The signed-integer forms convert each active L or Q source value to D. The operation uses 64-bit containers, reads the source from the low source-width field, and writes the D result to the complete container. Every inactive container retains its previous value.

A completed conversion accrues generated NV, OF, UF, and NX causes in FFLAGS; DZ is unchanged. An enabled generated cause raises FLOATING_POINT_EXCEPTION and suppresses destination and newly accrued FFLAGS effects.

Each 64-bit operation container reads its low half-precision source field. The active container writes a double-precision result, while the inactive container retains its old destination value.

VFCVTD.H half-to-double conversion containers

2.75in

Encodings

VFCVTD.{H|S}(z) Pn(p), Vn(v), Vn(w)

Format: Instruction format for VFCVTD.{H|S}(z) Pn(p), Vn(v), Vn(w)

Format: Instruction format for VFCVTD.{H|S}(z) Pn(p), Vn(v), Vn(w)

size — allowed: 0x1..0x2 [reserved_vector_element_type]

2.75in VFCVTD.{L|Q}(z) Pn(p), Vn(v), Vn(w)

Format: Instruction format for VFCVTD.{L|Q}(z) Pn(p), Vn(v), Vn(w)

Format: Instruction format for VFCVTD.{L|Q}(z) Pn(p), Vn(v), Vn(w)

size — allowed: 0x2..0x3 [reserved_vector_element_type]