REPcc

Operation

Repeats the next instruction while the counter and condition remain active.

Assembler Syntax

REPcc Rn(r), (<instruction>)

Privilege

Unprivileged

REPcc installs repeat state for the following single instruction. The selected counter register is interpreted as an unsigned remaining count. REP is the unconditional spelling and uses condition T. Condition F is reserved and is not a valid encoding. A faulting iteration does not decrement the count. A successful iteration decrements it before an event may be admitted. An event between iterations saves the repeat-prefix address and clears hidden repeat state; ERET returns to the prefix and restores no repeat continuation.

The body instruction is fetched, decoded, and checked for repeatability before the zero-count rule is applied. If the counter is zero, the decoded body is annulled and has no architectural side effects.

If the counter is nonzero, the first body iteration executes before any condition check. The repeat condition is tested against a temporary ZNCV image derived from the body instruction's repeat-observed value: Z reports zero, N is the most significant bit at the observation width, and C and V are zero. REPcc never uses architectural FLAGS as the condition input and does not write architectural FLAGS beyond any ordinary FLAGS effect of the body itself.

Body completion, observation, temporary-condition construction, architectural commit, counter decrement, and continuation PC selection are one precise atomic architectural commit step. An interrupt handler therefore cannot alter the continuation decision of an iteration that reached this step. Every completed body iteration decrements the counter by one, including the terminating condition-false iteration. Writes by the body to the selected counter register have no architectural effect while repeat state is active.

2.75in

Encodings

REPcc Rn(r), (<instruction>)

Format: Instruction format for REPcc Rn(r), (<instruction>)

cc — allowed: 0, 0x2..0xf [condition_false_reclaimed]