STP

Operation

Stores one canonical register pair as a 128-bit memory value.

Assembler Syntax

STP PAIRn(s), <ea>(e)

Privilege

Unprivileged

Required CPUID flags

STP

Stores the selected canonical register pair as one naturally aligned 16-byte memory value. The even register supplies bits 63:0 and the following odd register supplies bits 127:64. The two halves form one compound store; a preceding alignment or memory-access fault exposes no partial write.

2.75in

Encodings

STP PAIRn(s), <ea>(e)

Format: Instruction format for STP PAIRn(s), <ea>(e)

memory — excluded: immediate [memory_operand_required]