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VZIPHI

Operation

Interleave the upper halves of the old destination and source.

Assembler Syntax

VZIPHI.{B|W|L|Q}(z) Pn(p), Vn(v), Vn(w)

Privilege

Unprivileged

Required CPUID flags

VECTOR

VZIPHI forms each adjacent result-lane pair from one lane in the upper half of each input. In increasing order through those input halves, the even result lane receives the old destination value and the odd result lane receives the corresponding Vn value. The governing predicate retains the corresponding old destination value in each inactive result lane.

A right-to-left 128-bit W-lane example: result pairs alternate matching lanes from the upper halves of old Vd and source Vn, while inactive result lanes preserve old Vd.

VZIPHI.W upper-half interleave

2.75in

Encodings

VZIPHI.{B|W|L|Q}(z) Pn(p), Vn(v), Vn(w)

Format: Instruction format for VZIPHI.{B|W|L|Q}(z) Pn(p), Vn(v), Vn(w)

Format: Instruction format for VZIPHI.{B|W|L|Q}(z) Pn(p), Vn(v), Vn(w)