VSCATTER

Operation

Scatter governed vector lanes while journaling completed lanes in a predicate.

Assembler Syntax

VSCATTER.{B|W|L|Q}(z) Pn(p), Pn(c), Vn(v), [Rn(b) + Rn(s)]

VSCATTER.L Pn(p), Pn(c), Vn(v), [Vn(x)]

VSCATTER.Q Pn(p), Pn(c), Vn(v), [Vn(x)]

VSCATTER.{B|W|L|Q}(z) Pn(p), Pn(c), Vn(v), [Rn(b) + Vn(x)]

VSCATTER.{B|W|L|Q}(z) Pn(p), Pn(c), Vn(v), [Rn(b) + Vn(x) * <scale>]

VSCATTER.{B|W|L|Q}(z) Pn(p), Pn(c), Vn(v), [Rn(b) + Vn(x) * <scale> + <disp8s>]

VSCATTER.{B|W|L|Q}(z) Pn(p), Pn(c), Vn(v), [Rn(b) + Vn(x) * <scale> + <disp16s>]

VSCATTER.{B|W|L|Q}(z) Pn(p), Pn(c), Vn(v), [Rn(b) + Vn(x) * <scale> + <disp32s>]

VSCATTER.{B|W|L|Q}(z) Pn(p), Pn(c), Vn(v), [Rn(b) + Vn(x) * <scale> + <disp64>]

Privilege

Unprivileged

Required CPUID flags

VECTOR

Let \(E\) be the selected element width in bytes, \(N=VLEN/(8E)\), and \(G\) be the typed governing-predicate image whose significant bits are Pg[iE] for \(0\leq i<N\). Pg and Ps shall name different predicate registers. Before attempting a lane, VSCATTER replaces Ps by its typed image Ps AND G; all bits outside the typed predicate image are cleared.

If G AND NOT Ps is empty, the instruction completes normally with Ps == G. Otherwise it selects one pending lane \(i\), calculates that lane’s effective address from the selected address form, and issues exactly one \(E\)-byte normal-memory store of source lane \(i\) through the default data segment. On success it sets Ps[iE] and commits the store and completion bit at a lane-completion boundary. If more lanes remain pending, the PC continues to identify this VSCATTER and execution may admit an asynchronous event before another lane is attempted. A lane-completion boundary is not an instruction retirement or a debug-trace boundary.

Lane selection order is not architecturally specified. When stores from two lanes overlap in physical memory, the final value of each overlapping byte is therefore unspecified; every successful lane nevertheless performs exactly one \(E\)-byte store and sets its completion bit. A failure reported before the store’s point of no return leaves that bit clear and is retry-safe. A failure reported after the store becomes irrevocable sets the bit and defers an imprecise machine check to a subsequent boundary. Software emulation shall perform or explicitly waive the store before setting the completion bit. The address and source vector may name the same vector register. VSCATTER preserves FLAGS and is not permitted for MMIO.

2.75in

Encodings

VSCATTER.{B|W|L|Q}(z) Pn(p), Pn(c), Vn(v), [Rn(b) + Rn(s)]

Format: Instruction format for VSCATTER.{B|W|L|Q}(z) Pn(p), Pn(c), Vn(v), [Rn(b) + Rn(s)]