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VMULHU

Operation

Writes the high half of each active unsigned destination/source product.

Assembler Syntax

VMULHU.{B|W|L|Q}(z) Pn(p), Vn(v), Vn(w)

VMULHU.{B|W|L|Q}(z) Pn(p), <ea>(e), Vn(v)

VMULHU.{B|W|L|Q}(z) Pn(p), Vn(v), <ea>(e)

Privilege

Unprivileged

Required CPUID flags

VECTOR

The governing predicate selects destination elements for update. The old destination and corresponding source are interpreted as unsigned values at the selected B, W, L, or Q width. Their product is formed at twice that width, and its upper element-width half replaces the destination element. An unselected destination element retains its previous bit pattern.

The register form reads both operands from corresponding vector lanes. The memory-source form reads source elements from memory and updates destination register lanes. The memory-destination form treats each selected memory element as the old destination, multiplies it by the corresponding source-register lane, and writes the upper half back to that memory element.

2.75in

Encodings

VMULHU.{B|W|L|Q}(z) Pn(p), Vn(v), Vn(w)

Format: Instruction format for VMULHU.{B|W|L|Q}(z) Pn(p), Vn(v), Vn(w)

Format: Instruction format for VMULHU.{B|W|L|Q}(z) Pn(p), Vn(v), Vn(w)

2.75in VMULHU.{B|W|L|Q}(z) Pn(p), <ea>(e), Vn(v)

Format: Instruction format for VMULHU.{B|W|L|Q}(z) Pn(p), <ea>(e), Vn(v)

Format: Instruction format for VMULHU.{B|W|L|Q}(z) Pn(p), <ea>(e), Vn(v)

2.75in VMULHU.{B|W|L|Q}(z) Pn(p), Vn(v), <ea>(e)

Format: Instruction format for VMULHU.{B|W|L|Q}(z) Pn(p), Vn(v), <ea>(e)

Format: Instruction format for VMULHU.{B|W|L|Q}(z) Pn(p), Vn(v), <ea>(e)

dstexcluded: immediate [invalid_destination]