CMPXCHGP

Operation

Atomically compares and conditionally exchanges a 128-bit memory value using two register pairs.

Assembler Syntax

CMPXCHGP/order(o) PAIRn(x), PAIRn(d), <ea>(e)

Privilege

Unprivileged

Required CPUID flags

CMPXCHGP

Treats each canonical register pair as a 128-bit little-endian integer: the even register supplies bits 63:0 and the following odd register supplies bits 127:64. The instruction atomically reads a naturally aligned 16-byte memory value, compares it with the original expected pair, and stores the original desired pair only when both halves compare equal. In both cases the expected pair receives the old memory value. FLAGS.Z is set exactly when the store occurs; FLAGS.N, FLAGS.C, and FLAGS.V are cleared.

The encoded memory-order selector governs the complete operation on both outcomes under the same success and failure rules as CMPXCHG. An alignment or memory-access fault exposes no register, flag, or memory update.

2.75in

Encodings

CMPXCHGP/order(o) PAIRn(x), PAIRn(d), <ea>(e)

Format: Instruction format for CMPXCHGP/order(o) PAIRn(x), PAIRn(d), <ea>(e)

order — allowed: 0x0..0x4 [memory_order_reserved_reclaimed]

memory — excluded: immediate [memory_operand_required]