PZIPHI

Operation

Interleave the upper halves of two predicate-lane sequences.

Assembler Syntax

PZIPHI.{B|W|L|Q}(z) Pn(p), Pn(q), Pn(h)

Privilege

Unprivileged

Required CPUID flags

VECTOR

PZIPHI selects the upper half of the significant predicate lanes for the chosen B, W, L, or Q width from each source. In increasing order through those halves, each even result lane receives a left-source value and the following odd result lane receives the corresponding right-source value. The complete destination predicate image is written, and every bit outside its significant positions is cleared. The operation leaves FLAGS unchanged.

In this fixed 16-byte example, new Pd alternates typed predicate lanes from the upper halves of Pa and Pb. Larger VLEN begins at half its architectural typed lane count.

PZIPHI.W upper-half predicate interleave

2.75in

Encodings

PZIPHI.{B|W|L|Q}(z) Pn(p), Pn(q), Pn(h)

Format: Instruction format for PZIPHI.{B|W|L|Q}(z) Pn(p), Pn(q), Pn(h)

Format: Instruction format for PZIPHI.{B|W|L|Q}(z) Pn(p), Pn(q), Pn(h)