VMULHSU

Operation

Writes the high half of each active signed-destination by unsigned-source product.

Assembler Syntax

VMULHSU.{B|W|L|Q}(z) Pn(p), Vn(v), Vn(w)

VMULHSU.{B|W|L|Q}(z) Pn(p), <ea>(e), Vn(v)

VMULHSU.{B|W|L|Q}(z) Pn(p), Vn(v), <ea>(e)

Privilege

Unprivileged

Required CPUID flags

VECTOR

The governing predicate selects destination elements for update. At the selected B, W, L, or Q width, the old destination is interpreted as a two's-complement signed value and the corresponding source is interpreted as an unsigned value. Their product is formed at twice that width, and its upper element-width half replaces the destination element. An unselected destination element retains its previous bit pattern.

In the register form, the old destination-register lane is signed and the source-register lane is unsigned. In the memory-source form, the old destination-register lane is signed and the corresponding memory source is unsigned. In the memory-destination form, the old memory destination is signed and the corresponding source-register lane is unsigned; the upper half is written back to that memory element.

2.75in

Encodings

VMULHSU.{B|W|L|Q}(z) Pn(p), Vn(v), Vn(w)

Format: Instruction format for VMULHSU.{B|W|L|Q}(z) Pn(p), Vn(v), Vn(w)

2.75in VMULHSU.{B|W|L|Q}(z) Pn(p), <ea>(e), Vn(v)

Format: Instruction format for VMULHSU.{B|W|L|Q}(z) Pn(p), <ea>(e), Vn(v)

2.75in VMULHSU.{B|W|L|Q}(z) Pn(p), Vn(v), <ea>(e)

Format: Instruction format for VMULHSU.{B|W|L|Q}(z) Pn(p), Vn(v), <ea>(e)

dst — excluded: immediate [invalid_destination]