Architectural Time
Each logical processor owns one 64-bit invariant timebase. The value advances modulo \(2^{64}\) at the exact, nonzero integer number of ticks per second reported by CPUID TICKS_PER_SECOND. Its rate is independent of processor clock-frequency changes and the implementation-cycle counter. In particular, PMC.EN does not affect the timebase, and CYCLE is not an elapsed-time substitute.
The timebase continues to advance while the logical processor is halted or blocked by WAIT. RDTIME returns one atomic snapshot and is available in user and supervisor modes. Both modes observe the same value. The snapshot is elapsed-time state, not wall-clock or calendar time, and RDTIME is neither a memory access nor a memory fence.
Warm RESET preserves the timebase value and frequency. Cold reset initializes the value to zero and begins a new epoch; the architecture does not order values from different cold-reset epochs. The timebase and its deadline timer are per-logical-processor runtime resources, not task computational state, and no state-record instruction transfers them.
One-Shot Deadline Timer
Each logical processor owns one one-shot deadline timer consisting of armed state, an absolute timebase deadline, and a 24-bit interrupt identity. TARM and TCANCEL are the only architectural programming operations. The timer state has no control-register or state-record projection.
TARM observes the current time and classifies its absolute deadline by signed modular distance:
A positive distance arms the timer and atomically replaces any previous arm. Software can therefore schedule at most \(2^{63}-1\) ticks into the future with one operation. A zero or negative distance is already reached: TARM posts the supplied identity to the local interrupt file and leaves the timer disarmed. The supplied 64-bit identity value must be from 1 through ICAP.MAX_ID. An invalid identity raises INVALID_CONTROL_SELECTOR without changing timer state.
When time reaches an armed deadline, posting the configured identity and clearing armed state are one atomic transition. Expiry is one-shot; periodic behavior requires software to install another absolute deadline. TCANCEL atomically clears armed state and is a no-op when already disarmed. Neither TARM nor TCANCEL clears a pending bit created by an earlier expiry.
Expiry posts pending state regardless of the identity's enable bit, ITHRESH, STATUS.IE, ECR.V, or event depth. Those gates remain owned by the interrupt file and event-admission model. A halted logical processor leaves HALT only if the resulting interrupt becomes admissible; otherwise the identity remains pending. A WAIT may return spuriously so that an admissible interrupt can be processed, while time advancement and posting remain independent of that return.
Time advancement, expiry, TARM, TCANCEL, interrupt-file pending operations, and event-entry commit are observed in one of their legal serial orders. A cancellation ordered before expiry prevents the post; a cancellation ordered after expiry cannot remove it. An expiry ordered before replacement may leave the old identity pending, whereas a replacement ordered first prevents the superseded deadline from posting. No operation loses a post that has already committed. These operations do not by themselves order memory operations.
Warm and cold reset disarm the timer. Reset does not clear interrupt-file pending state except through the interrupt file's own reset transition.