RDPMC

Operation

Read the 64-bit performance counter selected by a constant counter ID.

Assembler Syntax

RDPMC <imm16>, Rn(d)

Privilege

Unprivileged

Performance-Counter IDs

RDPMC selects a 64-bit counter with its 16-bit immediate ID. The three standard counters are mandatory and wrap modulo \(2^{64}\). Cold reset and warm RESET clear them to zero. PMC.EN controls whether they increment.

Standard Performance Counters

ID	Name	Increment event
1	CYCLE	each implementation cycle while PMC.EN is set
2	INSTRET	each successfully committed architectural instruction
3	PTWALK	start of a hardware page walk after a paging-enabled TLB miss

Each successfully committed repeat-body iteration contributes one INSTRET event. A faulting instruction does not. PTWALK includes a walk that later reports a page fault, but excludes a segment-bound or canonical-address failure detected before a walk begins. ID zero is unavailable because index zero of the CPUID performance-counter leaf is its common discovery header. Other IDs beyond the standard set are implementation-defined and are discovered through that leaf.

Every privilege level may read every implemented counter. Clearing PMC.EN freezes the current counter values without clearing them.

2.75in

Encodings

RDPMC <imm16>, Rn(d)

Format: Instruction format for RDPMC <imm16>, Rn(d)