VGATHER

Operation

Gather governed vector lanes while journaling completed lanes in a predicate.

Assembler Syntax

VGATHER.{B|W|L|Q}(z) Pn(p), Pn(c), [Rn(b) + Rn(s)], Vn(v)

VGATHER.L Pn(p), Pn(c), [Vn(x)], Vn(v)

VGATHER.Q Pn(p), Pn(c), [Vn(x)], Vn(v)

VGATHER.{B|W|L|Q}(z) Pn(p), Pn(c), [Rn(b) + Vn(x)], Vn(v)

VGATHER.{B|W|L|Q}(z) Pn(p), Pn(c), [Rn(b) + Vn(x) * <scale>], Vn(v)

VGATHER.{B|W|L|Q}(z) Pn(p), Pn(c), [Rn(b) + Vn(x) * <scale> + <disp8s>], Vn(v)

VGATHER.{B|W|L|Q}(z) Pn(p), Pn(c), [Rn(b) + Vn(x) * <scale> + <disp16s>], Vn(v)

VGATHER.{B|W|L|Q}(z) Pn(p), Pn(c), [Rn(b) + Vn(x) * <scale> + <disp32s>], Vn(v)

VGATHER.{B|W|L|Q}(z) Pn(p), Pn(c), [Rn(b) + Vn(x) * <scale> + <disp64>], Vn(v)

Privilege

Unprivileged

Required CPUID flags

VECTOR

Let \(E\) be the selected element width in bytes, \(N=VLEN/(8E)\), and \(G\) be the typed governing-predicate image whose significant bits are Pg[iE] for \(0\leq i<N\). Pg and Ps shall name different predicate registers. Before attempting a lane, VGATHER replaces Ps by its typed image Ps AND G; all bits outside the typed predicate image are cleared. Thus completed lanes that are no longer governed are discarded.

If G AND NOT Ps is empty, the instruction completes normally with Ps == G. Otherwise it selects one pending lane \(i\), calculates that lane’s effective address from the selected address form, and issues exactly one \(E\)-byte normal-memory load through the default data segment. On success it replaces only destination lane \(i\), sets Ps[iE], and commits those effects at a lane-completion boundary. If more lanes remain pending, the PC continues to identify this VGATHER and execution may admit an asynchronous event before another lane is attempted. A lane-completion boundary is not an instruction retirement or a debug-trace boundary.

A synchronous memory fault commits no destination value and does not set the faulting lane’s completion bit; the typed normalization of Ps remains committed, so retrying at the saved PC does not repeat an already completed lane. Software emulation of a faulting lane shall write the destination lane before setting its completion bit. The vector address and destination operands shall not name the same vector register. VGATHER preserves FLAGS and is not permitted for MMIO.

2.75in

Encodings

VGATHER.{B|W|L|Q}(z) Pn(p), Pn(c), [Rn(b) + Rn(s)], Vn(v)

Format: Instruction format for VGATHER.{B|W|L|Q}(z) Pn(p), Pn(c), [Rn(b) + Rn(s)], Vn(v)

govern, completion — illegal_instruction

2.75in VGATHER.L Pn(p), Pn(c), [Vn(x)], Vn(v)

Format: Instruction format for VGATHER.L Pn(p), Pn(c), [Vn(x)], Vn(v)

govern, completion — illegal_instruction

address, dst — illegal_instruction

2.75in VGATHER.Q Pn(p), Pn(c), [Vn(x)], Vn(v)

Format: Instruction format for VGATHER.Q Pn(p), Pn(c), [Vn(x)], Vn(v)

govern, completion — illegal_instruction

address, dst — illegal_instruction

2.75in VGATHER.{B|W|L|Q}(z) Pn(p), Pn(c), [Rn(b) + Vn(x)], Vn(v)

Format: Instruction format for VGATHER.{B|W|L|Q}(z) Pn(p), Pn(c), [Rn(b) + Vn(x)], Vn(v)

govern, completion — illegal_instruction

address, dst — illegal_instruction

2.75in VGATHER.{B|W|L|Q}(z) Pn(p), Pn(c), [Rn(b) + Vn(x) * <scale>], Vn(v)

Format: Instruction format for VGATHER.{B|W|L|Q}(z) Pn(p), Pn(c), [Rn(b) + Vn(x) * <scale>], Vn(v)

govern, completion — illegal_instruction

address, dst — illegal_instruction

2.75in VGATHER.{B|W|L|Q}(z) Pn(p), Pn(c), [Rn(b) + Vn(x) * <scale> + <disp8s>], Vn(v)

Format: Instruction format for VGATHER.{B|W|L|Q}(z) Pn(p), Pn(c), [Rn(b) + Vn(x) * <scale> + <disp8s>], Vn(v)

govern, completion — illegal_instruction

address, dst — illegal_instruction

2.75in VGATHER.{B|W|L|Q}(z) Pn(p), Pn(c), [Rn(b) + Vn(x) * <scale> + <disp16s>], Vn(v)

Format: Instruction format for VGATHER.{B|W|L|Q}(z) Pn(p), Pn(c), [Rn(b) + Vn(x) * <scale> + <disp16s>], Vn(v)

govern, completion — illegal_instruction

address, dst — illegal_instruction

2.75in VGATHER.{B|W|L|Q}(z) Pn(p), Pn(c), [Rn(b) + Vn(x) * <scale> + <disp32s>], Vn(v)

Format: Instruction format for VGATHER.{B|W|L|Q}(z) Pn(p), Pn(c), [Rn(b) + Vn(x) * <scale> + <disp32s>], Vn(v)

govern, completion — illegal_instruction

address, dst — illegal_instruction

2.75in VGATHER.{B|W|L|Q}(z) Pn(p), Pn(c), [Rn(b) + Vn(x) * <scale> + <disp64>], Vn(v)

Format: Instruction format for VGATHER.{B|W|L|Q}(z) Pn(p), Pn(c), [Rn(b) + Vn(x) * <scale> + <disp64>], Vn(v)

govern, completion — illegal_instruction

address, dst — illegal_instruction