System Target Interface

The compiler emits the requested architectural operation; runtime privilege and policy checks remain active.

System-Register Builtins


Header:	`<bedrocksysregintrin.h>`

System-Register Intrinsics

Name	C interface	Lowering	Availability, constraint, and effect
`read_code_segment`	`u64(void)`	`RDSEG CS`	Unprivileged; reads the current CS image through the dedicated source-only encoding.
`read_control_register`	`u64(control_register)`	`RDCR`	Supervisor; selector is a constant in 0 through 65535 naming a defined register.
`read_segment_register`	`u64(segment_register)`	`RDSEG`	Unprivileged; selector is a compile-time `__bedrock_segment_register_t`.
`write_control_register`	`void(control_register,u64)`	`WRCR`	Supervisor; defined constant selector required; writes the register and clobbers memory.
`write_segment_register`	`void(segment_register,u64)`	`WRSEG`	Unprivileged; validates the SREG image, changes address interpretation, and fully clobbers memory.
`write_status`	`void(u16)`	`WRSTATUS`	Supervisor; reserved and privilege-controlled bits follow the ISA; compiler-visible side effect.

The system-register header defines __bedrock_control_register_t constants for every published control-register selector. The constants are names for the architectural selector values; they do not weaken the privilege, reserved-bit, or per-register validation performed by RDCR and WRCR.

It also defines the pure value macros __BEDROCK_SEGMENT_IMAGE, __BEDROCK_SEGMENT_IMAGE_FOR_BASE, and __BEDROCK_SEGMENT_DISABLED. They construct 64-bit segment images without reading or writing architectural state.

__BEDROCK_SEGMENT_IMAGE(base_page,exponent,mantissa, bounds_only) places the low 52, 5, and 6 bits of the first three operands in their architectural fields and normalizes bounds_only to zero or one. Each operand is evaluated once. A valid enabled image uses an exponent from 0 through 31 and a mantissa from 1 through 63. The macro only packs fields; it does not validate the resulting base, span, limit, or address canonicality.

__BEDROCK_SEGMENT_IMAGE_FOR_BASE(base,...) encodes \(\lfloor\texttt{(uint64\_t)base}/4096\rfloor\) in the base-page field. It discards the low 12 bits, so a misaligned operand names the containing page and does not preserve the original byte address. The macro imposes no alignment precondition and does not adjust a later offset to compensate for the discarded bits. __BEDROCK_SEGMENT_DISABLED is the canonical all-zero disabled image.

Cache-Management Builtins


Header:	`<bedrockcacheintrin.h>`

All cache range operations evaluate the address once and obtain the maintenance granule from CPUID CACHE_TOPOLOGY. A zero length emits no cache-maintenance instruction. A nonzero, nonwrapping byte range selects every maintenance block that intersects the range and lowers to one block instruction per selected block. Each instruction translates its own block address. If a later instruction faults, blocks completed by earlier instructions remain completed.

For a nonzero length, the mathematical half-open range \([\mathrm{address},\mathrm{address}+\mathrm{length})\) shall lie within the 64-bit address space. Otherwise the behavior of the call is undefined and no architectural cache-maintenance sequence is required. An implementation may diagnose a provably wrapping constant range. A valid range end is calculated mathematically, not modulo \(2^{64}\).

Cache-Management Intrinsics

Name	C interface	Lowering	Availability, constraint, and effect
`flush_dcache`	`void(void *,size_t)`	`FLSHDCACHE`	Supervisor; applies FLSHDCACHE to every CPUID maintenance block intersecting the range and fully clobbers memory.
`invalidate_dcache`	`void(void *,size_t)`	`INVDCACHE`	Supervisor; applies INVDCACHE to every CPUID maintenance block intersecting the range and fully clobbers memory.
`invalidate_icache`	`void(void *,size_t)`	`INVICACHE`	Supervisor; applies local INVICACHE to every CPUID maintenance block intersecting the range, serializes instruction fetch, and fully clobbers memory.
`sync_cache`	`void(void *,size_t)`	`SYNCCACHE`	Supervisor; applies SYNCCACHE to every CPUID maintenance block intersecting the range, serializes instruction fetch, and fully clobbers memory.
`writeback_dcache`	`void(void *,size_t)`	`WRBKDCACHE`	Supervisor; applies WRBKDCACHE to every CPUID maintenance block intersecting the range and fully clobbers memory.

MMU Builtins


Header:	`<bedrockmmuintrin.h>`

MMU Intrinsics

Name	C interface	Lowering	Availability, constraint, and effect
`invalidate_asid`	`void(u16)`	`INVASID`	Supervisor; ASID is a constant in 0 through 65535 and the operation fully clobbers memory.
`invalidate_page`	`void(const void *)`	`INVPAGE`	Supervisor; argument supplies a linear address and invalidates any matching cached leaf mapping containing it; the operation fully clobbers memory.
`invalidate_tlb`	`void(void)`	`INVTLB`	Supervisor; translation-state side effect and full memory clobber.
`page_table_query`	`query_result(u32,u64)`	`PTQUERY`	Supervisor; level is an integer constant expression in 1 through 5; wrapper atomically returns value and `FLAGS`; page walk without access to the queried C object.
`switch_page_table`	`void(u64)`	`SWPT`	Supervisor; valid page-table image required; changes address space and fully clobbers memory.
`switch_page_table_asid`	`void(u64,u16)`	`SWPTA`	Supervisor; valid image and low 16-bit ASID; changes address space and fully clobbers memory.
`virtual_to_physical`	`query_result(u64)`	`VTOP`	Supervisor; wrapper returns value and operation-defined `FLAGS` captured atomically; page walk without access to the translated C object.