General Instructions

Summary

General Instructions Summary (Informative)

Mnemonic	Brief description
	Replaces the destination with its selected-width two's-complement absolute value.
	Adds source and carry-in to the destination, writes the modular sum, and updates ZNCV.
	Adds the source operand to the destination operand.
	Order prior memory operations before later memory operations.
	Computes the bitwise AND of the source and destination operands.
	Toggles the indexed destination bit, sets Z when it was clear, and clears NCV.
	Extracts a contiguous bitfield and sign-extends it.
	Extracts a contiguous bitfield and zero-extends it.
	Inserts low source bits into a contiguous destination bitfield.
	Clears the indexed destination bit, sets Z when it was clear, and clears NCV.
	Clears destination bits selected by the source operand.
	Raise the breakpoint exception.
	Checks signed value membership in the inclusive-inclusive interval [lo, hi].
	Checks signed value membership in the inclusive-exclusive interval [lo, hi).
	Checks signed value membership in the exclusive-inclusive interval (lo, hi].
	Checks signed value membership in the exclusive-exclusive interval (lo, hi).
	Checks unsigned value membership in the inclusive-inclusive interval [lo, hi].
	Checks unsigned value membership in the inclusive-exclusive interval [lo, hi).
	Checks unsigned value membership in the exclusive-inclusive interval (lo, hi].
	Checks unsigned value membership in the exclusive-exclusive interval (lo, hi).
	Sets the indexed destination bit, sets Z when it was clear, and clears NCV.
	Tests the indexed destination bit without writing it, sets Z when it is clear, and clears NCV.
	Pushes the continuation PC and atomically transfers control to the validated target.
	Performs a call when the condition is true.
	Writes the low selected-width half of the carryless source-by-destination product.
	Writes the high selected-width half of the carryless source-by-destination product.
	Writes zero to the selected-width destination.
	Atomically discards the resident continuation without changing the CFI key.
	Counts leading one bits in the selected-width source and writes the count.
	Counts leading zero bits in the selected-width source and writes the count.
	Computes a comparison result and updates condition codes without storing the temporary value.
	Compares two Rn registers and branches on the selected condition without writing FLAGS.
	Atomically compares memory with the expected register, conditionally stores, and returns the observed value.
	Atomically compares and conditionally exchanges a 128-bit memory value using two register pairs.
	Queries architectural discovery information through a selected Rn register.
	Updates a 32-bit CRC accumulator with selected source bytes.
	Updates a 32-bit CRC-32C accumulator with selected source bytes.
	Counts trailing one bits in the selected-width source and writes the count.
	Counts trailing zero bits in the selected-width source and writes the count.
	Decrements the selected-width destination modulo its width without changing FLAGS.
	Decrements the destination operand and updates integer FLAGS.
	Divides a signed quotient-register dividend by source and writes quotient and remainder registers.
	Divides an unsigned quotient-register dividend by source and writes quotient and remainder registers.
	Divides the signed destination by source with truncation toward zero and writes the quotient.
	Divides the unsigned destination by source and writes the quotient.
	Decrements the counter and branches only when its new value is nonzero and the condition is true.
	Return through a staged user context or from an architectural event.
	Extracts a selected-width value from a concatenated pair of Rn registers.
	Installs a resident continuation and transfers without return-record memory traffic.
	Sign-extends the selected source width to a longword EA destination.
	Sign-extends the selected source width to a quadword destination.
	Sign-extends a byte source to a word EA destination.
	Zero-extends the selected source width to a longword EA destination.
	Zero-extends the selected source width to a quadword destination.
	Zero-extends a byte source to a word EA destination.
	Atomically adds source to memory and returns the old memory value in the source register.
	Atomically ANDs source with memory and returns the old memory value in the source register.
	Atomically clears memory bits selected by a source and returns the old value.
	Atomically stores the signed maximum of memory and source and returns the old value.
	Atomically stores the unsigned maximum of memory and source and returns the old value.
	Atomically stores the signed minimum of memory and source and returns the old value.
	Atomically stores the unsigned minimum of memory and source and returns the old value.
	Atomically ORs source with memory and returns the old memory value in the source register.
	Atomically subtracts source from memory and returns the old memory value in the source register.
	Atomically exchanges a register with memory and returns the old memory value.
	Atomically XORs source with memory and returns the old memory value in the source register.
	Write back and invalidate one cache-maintenance block.
	Halt the executing logical processor until an asynchronous architectural event is admitted.
	Increments the index and branches only when it differs from the bound and the condition is true.
	Raise illegal-instruction exception.
	Increments the selected-width destination modulo its width without changing FLAGS.
	Increments the destination operand and updates integer FLAGS.
	Invalidate TLB entries for ASID.
	Invalidate one data-cache maintenance block.
	Invalidate one local instruction-cache maintenance block.
	Invalidate TLB mapping containing a linear address.
	Invalidate all TLB entries.
	Transfers control when the encoded condition is true.
	Transfers control to the target address.
	Pushes a long return frame and atomically transfers control to a new CS:PC pair.
	Loads one 128-bit memory value into a canonical register pair.
	Computes the source effective address without reading memory and writes it to the destination.
	Atomically transfers control to a new CS:PC pair.
	Pops a long return frame and atomically restores CS:PC.
	Adds the low product of two sources to the destination.
	Writes the signed greater of source and destination to the destination.
	Writes the unsigned greater of source and destination to the destination.
	Writes the signed lesser of source and destination to the destination.
	Writes the unsigned lesser of source and destination to the destination.
	Writes the signed remainder of destination-by-source truncation-toward-zero division.
	Writes the unsigned remainder of destination-by-source division.
	Copies the source operand to the destination operand.
	Loads from memory with acquire ordering.
	Copies source to destination only when the encoded condition is true.
	Copies from a current-domain source to user-domain memory.
	Stores an Rn register value to memory with a non-temporal access hint.
	Stores to memory with release ordering.
	Copies from user-domain memory to a current-domain destination.
	Copies from user-domain memory to user-domain memory.
	Subtracts the low product of two sources from the destination.
	Multiplies the destination by the source and keeps the low half.
	Writes the high half of the signed 64-bit source-by-destination product.
	Writes the high half of the signed-destination by unsigned-source 64-bit product.
	Writes the high half of the unsigned 64-bit source-by-destination product.
	Writes the selected-width two's-complement negation of the destination.
	No architectural state change.
	Writes the selected-width bitwise complement of the destination.
	Computes the bitwise OR of the source and destination operands.
	Computes operand parity and writes the predicate to an Rn register.
	Pops one 64-bit stack value into an Rn or SREG destination.
	Counts set bits in the selected-width source and writes the count.
	Pops one canonical Rn register pair selected by an inline pair index.
	Hints that EA will be read soon; faults only under the configured prefetch-fault policy.
	Hint that EA will be read with non-temporal locality.
	Reads the selected raw page-table descriptor without changing translation state.
	Pushes one Rn register value, SREG image, or the current CS image onto the stack.
	Pushes one canonical Rn register pair selected by an inline pair index.
	Read a privileged control register.
	Read the integer condition-code flags into an Rn register.
	Read the 64-bit performance counter selected by a constant counter ID.
	Read one atomic snapshot of the invariant architectural timebase.
	Read an SREG or the current CS image into an Rn register.
	Read the processor STATUS register into an Rn register.
	Repeats the next instruction while the counter and condition remain active.
	Perform warm reset; preserve BOOTPC and BOOTCFG.
	Restores the base user-state record.
	Pops and validates a return PC, then atomically advances SP and transfers control.
	Reverses bit order within the selected operand width.
	Reverses byte order within the selected operand width and writes the result.
	Order prior reads before later reads.
	Rotates the destination left by the count modulo the selected width without changing FLAGS.
	Rotates the destination right by the count modulo the selected width without changing FLAGS.
	Arithmetic-right-shifts the destination by the count modulo its selected width without changing FLAGS.
	Saves the base user-state record.
	Subtracts source and C borrow from destination, writes the modular difference, and updates ZNCV.
	Restores the base supervisor-state record.
	Saves the base supervisor-state record.
	Computes segment pre-translation of the effective-address point and reports bounds failure in FLAGS.
	Writes integer one to the destination operand.
	Writes one or zero to the destination according to the encoded condition.
	Replaces integer FLAGS from an immediate bitmap.
	Prevents younger instructions from executing speculatively across the fence.
	Left-shifts the destination by the count modulo its selected width without changing FLAGS.
	Logical-right-shifts the destination by the count modulo its selected width without changing FLAGS.
	Subtracts the source operand from the destination operand.
	Stores one canonical register pair as a 128-bit memory value.
	Atomically installs PTCR and clears ASCR as a page-table switch.
	Switches the page table and enables address-space context matching.
	Synchronize one cache-maintenance block for local instruction fetch.
	Raise the SYSTEM_CALL architectural event.
	Atomically install an absolute deadline and interrupt identity.
	Atomically disarm the current deadline timer.
	Computes a bitwise conjunction and updates condition codes without storing the temporary value.
	Tests two Rn registers and branches on the selected condition without writing FLAGS.
	Records a marker and instruction boundary in the implementation trace stream.
	Queries the current translation of a linear address without changing translation state.
	Permits a finite implementation-selected delay, including zero.
	Order prior writes before later writes.
	Write back one data-cache maintenance block.
	Write a privileged control register from an Rn register.
	Write the integer condition-code flags from an Rn register.
	Write an SREG segment image from an Rn register.
	Write the processor STATUS register from an Rn register.
	Exchanges selected-width operand values, committing both destinations together.
	Computes the bitwise XOR of the source and destination operands.
	Hints that the current logical processor may be deprioritized.