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Overview

Architecture and ABI Layers

Manual Scope

This manual defines programmer-visible architectural state, operand encoding, execution semantics, and instruction behavior for the Bedrock instruction set architecture.

Architectural Profile

Bedrock defines sixteen 64-bit general-purpose registers, R0 through R15. SP and PC are special architectural registers outside the Rn namespace, with SP-relative addressing tied to SS and PC-relative addressing tied to CS.

  • The PC names a byte in the instruction stream; sequential execution advances it by the encoded instruction length determined during decoding.

  • Encoded instruction length is explicit and bounded; the base profile defines encoded instruction lengths from 1 to 18 bytes.

  • Four integer operation sizes: B, W, L, and Q.

  • The optional scalable-vector extension provides 32 VLEN-bit vector registers and 16 packed predicate registers; VLEN is a reset-stable power of two from 128 through 2048 bits.

  • The effective-address model covers register, memory, immediate, absolute, segment-qualified, indexed, and auto-update operands.

  • Segment pre-translation precedes optional page-table translation.

  • User and supervisor modes share the instruction set, with privileged instructions and checked user-access moves defining supervisor-only behavior.

Normative Material and Specificity

Architecture prose, ordered steps, architecture tables, instruction encoding diagrams, and the Operation and Detailed Semantics fields of instruction entries are normative unless a section explicitly identifies material as a summary, example, or validation status.

Rule set or provider Covered material
Instruction definitions Concrete instruction encodings, operand and effective-address grammar, extension wiring, and document ordering.
Instruction Execution Model common rules and instruction-entry Operation and Detailed Semantics Executable instruction behavior, architectural state transitions, fault and commit ordering, repeat and architectural-event behavior, and single-logical-processor memory-access sequencing.
Formal memory model Permitted cross-logical-processor ordering and visibility.
ABI specifications ELF, C ABI, and calling-convention contracts.
Compiler-interface specifications Source-language and compiler-facing target-interface contracts.
External numerical floating-point providers Numerical results and certificates only; input validation and the resulting architectural trap or commit behavior follow the applicable Instruction Execution Model common rules and instruction entry's Operation and Detailed Semantics.

Presented material remains normative where declared and follows the applicable rule set. For executable behavior, readers apply the Instruction Execution Model common rules together with the applicable instruction entry's Operation and Detailed Semantics. The following specificity rules govern narrowing among applicable rules:

  1. Opcode-space length, required instruction length, encoded instruction length, field values, and decoding validity follow the selected instruction encoding, its field constraints, and the Instruction Encoding and Effective Addressing chapters.

  2. Execution of a decoded instruction follows its Operation and Detailed Semantics. An instruction-specific rule narrows the common execution, operand, flag, memory, or event rule that it names.

  3. Common architectural behavior follows the chapter that defines that behavior. A structure-specific rule narrows only the common rule that it names.

  4. Summary tables and examples provide navigation or explanatory context and do not replace a normative rule.

Two normative statements at the same specificity are required to agree. A discrepancy at that level is a specification defect and is resolved by correcting the normative sources and their derived tables together.