BFEXTU

Operation

Extracts a contiguous bitfield and zero-extends it.

Assembler Syntax

BFEXTU.{B|W|L|Q}(z) imm6(l), imm6(w), Rn(s), Rn(d)

Privilege

Unprivileged

Required CPUID flags

BFEXTU

Repeat eligibility

REP eligible; REPcc observes dst

Extracts extttimm6(w)+1 bits beginning at bit extttimm6(l) of the selected-width source and writes the zero-extended field to the destination. An encoding is invalid when the selected field extends past the operand width.

2.75in

Encodings

BFEXTU.{B|W|L|Q}(z) imm6(l), imm6(w), Rn(s), Rn(d)

Format: Instruction format for BFEXTU.{B|W|L|Q}(z) imm6(l), imm6(w), Rn(s), Rn(d)