VFCVTH

Operation

Converts active single-precision, double-precision, or signed integer elements to half precision.

Assembler Syntax

VFCVTH.{S|D}(z) Pn(p), Vn(v), Vn(w)

VFCVTH.{L|Q}(z) Pn(p), Vn(v), Vn(w)

Privilege

Unprivileged

Required CPUID flags

FP

VECTOR

VECTORFP

Each active S or D source value is converted to H. The signed-integer forms convert each active L or Q source value to H. The operation container is the larger of the source and 16-bit destination widths. The H result replaces the low 16-bit field; the other bits of an active destination container and every inactive container retain their previous values.

A completed conversion accrues generated NV, OF, UF, and NX causes in FFLAGS; DZ is unchanged. An enabled generated cause raises FLOATING_POINT_EXCEPTION and suppresses destination and newly accrued FFLAGS effects.

Each 64-bit operation container reads one double-precision source. The active container writes a half-precision result into its low field and retains the other destination bits; the inactive container remains unchanged.

VFCVTH.D double-to-half conversion containers

2.75in

Encodings

VFCVTH.{S|D}(z) Pn(p), Vn(v), Vn(w)

Format: Instruction format for VFCVTH.{S|D}(z) Pn(p), Vn(v), Vn(w)

Format: Instruction format for VFCVTH.{S|D}(z) Pn(p), Vn(v), Vn(w)

size — allowed: 0x2..0x3 [reserved_vector_element_type]

2.75in VFCVTH.{L|Q}(z) Pn(p), Vn(v), Vn(w)

Format: Instruction format for VFCVTH.{L|Q}(z) Pn(p), Vn(v), Vn(w)

Format: Instruction format for VFCVTH.{L|Q}(z) Pn(p), Vn(v), Vn(w)

size — allowed: 0x2..0x3 [reserved_vector_element_type]