VOR

Operation

Applies bitwise OR to corresponding active vector elements.

Assembler Syntax

VOR.{B|W|L|Q}(z) Pn(p), Vn(v), Vn(w)

VOR.{B|W|L|Q}(z) Pn(p), <ea>(e), Vn(v)

VOR.{B|W|L|Q}(z) Pn(p), Vn(v), <ea>(e)

Privilege

Unprivileged

Required CPUID flags

VECTOR

The register form computes the selected-width bitwise OR of each active source lane and corresponding old destination lane, then writes the result to the destination. When memory is the source, each active memory element is ORed with the corresponding old destination lane. In both forms, an inactive destination lane retains its previous value.

The memory-destination form reads each active destination element, computes its selected-width bitwise OR with the corresponding source-register lane, and writes the result back to the same element. An inactive memory element remains unchanged.

2.75in

Encodings

VOR.{B|W|L|Q}(z) Pn(p), Vn(v), Vn(w)

Format: Instruction format for VOR.{B|W|L|Q}(z) Pn(p), Vn(v), Vn(w)

2.75in VOR.{B|W|L|Q}(z) Pn(p), <ea>(e), Vn(v)

Format: Instruction format for VOR.{B|W|L|Q}(z) Pn(p), <ea>(e), Vn(v)

2.75in VOR.{B|W|L|Q}(z) Pn(p), Vn(v), <ea>(e)

Format: Instruction format for VOR.{B|W|L|Q}(z) Pn(p), Vn(v), <ea>(e)

dst — excluded: immediate [invalid_destination]