Floating-Point Instructions

Summary

Floating-Point Instructions Summary (Informative)

Mnemonic	Brief description
	Clears the selected floating-point source sign and writes its magnitude.
	Adds the source operand to the destination operand.
	Checks floating-point value membership in the inclusive-inclusive interval [lo, hi].
	Checks floating-point value membership in the inclusive-exclusive interval [lo, hi).
	Checks floating-point value membership in the exclusive-inclusive interval (lo, hi].
	Checks floating-point value membership in the exclusive-exclusive interval (lo, hi).
	Rounds a floating-point source toward positive infinity in the selected format.
	Classifies an S- or D-format source into a one-hot integer bitmap without changing FFLAGS.
	Writes positive zero to the complete 64-bit floating-point destination.
	Compares two floating-point operands and writes their relation to integer condition flags.
	Combines a magnitude source with the sign bit of a separate floating-point source.
	Converts between D and signed B/W/L/Q integer or H/S floating-point representations.
	Converts between H and signed B/W/L/Q integer or S/D floating-point representations.
	Converts between S and signed B/W/L/Q integer or H/D floating-point representations.
	Converts between D and unsigned B/W/L/Q integers.
	Converts between H and unsigned B/W/L/Q integers.
	Converts between S and unsigned B/W/L/Q integers.
	Divides the destination value by the source under the floating-point environment.
	Rounds a floating-point source toward negative infinity in the selected format.
	Converts the source encoding's signed exponent to the selected floating-point format.
	Produces the normalized significand view of a floating-point source.
	Rounds a floating-point source to an integral value using FSTATUS.RM.
	Rounds a floating-point source toward zero to an integral value.
	Computes the source product plus the old destination as one fused operation and rounds once.
	Selects the greater numeric source or destination value using IEEE NaN and zero rules.
	Selects the lesser numeric source or destination value using IEEE NaN and zero rules.
	Computes the destination modulo the source using a quotient truncated toward zero.
	Copies the source operand to the destination operand.
	Copies a floating-point source only when the encoded integer condition is true.
	Loads a named architectural binary64 constant selected by an unsigned 16-bit ID.
	Computes the source product minus the old destination as one fused operation and rounds once.
	Multiplies the source and destination values under the floating-point environment.
	Complements the selected floating-point source sign bit.
	Computes the negated source product minus the old destination as one fused operation and rounds once.
	Computes the old destination minus the source product as one fused operation and rounds once.
	Pops one canonical floating-point register pair selected by an inline pair index.
	Pushes one canonical floating-point register pair selected by an inline pair index.
	Computes the destination remainder using a nearest-even integral quotient.
	Restores the floating-point user-state record.
	Rounds a floating-point source to a nearest-even integral value independently of FSTATUS.RM.
	Saves the floating-point user-state record.
	Scales the destination by a power of two derived from the rounded source.
	Computes the selected-format square root of a floating-point source.
	Subtracts the source operand from the destination operand.
	Compares a floating-point source with positive zero and writes integer condition flags.
	Rounds a floating-point source toward zero in the same format.
	Exchanges the complete 64-bit images of two floating-point registers.
	Read the accrued floating-point exception flags into an Rn register.
	Read the FPU status/control register into an Rn register.
	Write the accrued floating-point exception flags from an Rn register.
	Write the FPU status/control register from an Rn register.

Common Floating-Point Semantics

The S and D suffixes select 32- and 64-bit floating-point scalar arithmetic sizes. H selects the 16-bit scalar conversion and storage format only. Conditional floating-point moves place the integer condition suffix in the mnemonic.

The H, S, and D formats are IEEE-754 binary16, binary32, and binary64. H uses sign bit 15, exponent bits 14..10, and fraction bits 9..0. S uses sign bit 31, exponent bits 30..23, and fraction bits 22..0. D uses sign bit 63, exponent bits 62..52, and fraction bits 51..0. An all-ones exponent and nonzero fraction is a NaN. The most significant fraction bit distinguishes a quiet NaN from a signaling NaN: zero is signaling and one is quiet. The architectural default quiet NaNs are 0x7e00 for H, 0x7fc00000 for S, and 0x7ff8000000000000 for D. Figure [fig:floating-point-register-encodings] shows both encodings in their 64-bit Fn register view.

An H conversion reads bits 15..0 of an H-valued Fn operand and an H result write writes zero to bits 63..16. An S operation reads bits 31..0 of each Fn operand. Writing an S result to Fn writes the result to bits 31..0 and writes zero to bits 63..32. A D operation reads and writes all 64 bits. Operations use the selected format for their intermediate and final values. FMADD, FMSUB, FNMADD, and FNMSUB form the complete multiply-add expression with unbounded intermediate range and precision and round only the final result. Other arithmetic operations round once after computing their exact mathematical result.

An encoded FEA source immsf is an exact IEEE 754 binary32 payload, and immdf is an exact binary64 payload. Either immediate may be used by either an S or D instruction. If the payload format differs from the operation format selected by the suffix, the source is converted to the operation format using the current FSTATUS.RM before the operation. All conversion causes, including causes from NaN handling and narrowing, are combined with the operation's causes. The combined cause set follows the same enabled-cause fault test, FFLAGS accrual, and all-or-nothing destination commit rules below. Floating-point immediate forms are source-only.

Input, NaN, Rounding, and Result Order

Each ordinary floating-point operation applies the following order.

1. Read all operands and classify zero, subnormal, normal, infinity, quiet NaN, and signaling NaN.

2. If FSTATUS.DAZ is set, replace each subnormal input with a zero having the same sign.

3. Determine signaling-NaN and operation-specific floating-point exception causes and form the exact mathematical result.

4. For a NaN result, select the first signaling NaN in source-operand order, or the first quiet NaN when there is no signaling NaN, and set its quiet bit. If the operation produces a NaN without a NaN operand, use the default quiet NaN. When FSTATUS.DN is set, replace the selected NaN with the default quiet NaN.

5. Round a numeric result to the selected format using FSTATUS.RM, except where an instruction names a fixed rounding direction.

6. Detect overflow and tininess after rounding. UF is generated when the rounded result is tiny and inexact.

7. If FSTATUS.FTZ is set and the rounded result is a nonzero subnormal, replace it with a zero of the same sign and generate both UF and NX.

8. Test all generated causes against their FSTATUS enable bits and then perform the architectural commit.

A signaling NaN generates NV. A quiet NaN does not generate NV unless the operation itself is invalid. When two NaN operands have the same priority, source-operand order determines the selected sign and payload. Quieting sets the quiet bit and preserves the remaining selected sign and payload bits.

Overflow generates OF and NX. Nearest-even produces signed infinity. Toward zero produces the signed maximum finite value. Toward positive produces positive infinity for a positive result and the negative maximum finite value for a negative result. Toward negative produces negative infinity for a negative result and the positive maximum finite value for a positive result.

Floating-Point Exception Causes and Commit

Cause	Generated when
NV	an input is a signaling NaN; an arithmetic operation has no defined numeric result, including infinity minus the same infinity, zero times infinity, zero divided by zero, infinity divided by infinity, or square root of a negative nonzero value; or a floating-to-integer conversion is invalid
DZ	a finite nonzero value is divided by zero
OF	the rounded numeric magnitude exceeds the selected format's finite range
UF	the result is tiny after rounding and inexact, or FTZ flushes a nonzero subnormal result
NX	rounding or a valid conversion changes the exact value, or OF or FTZ generates NX

If any generated floating-point exception cause has its matching FSTATUS enable bit set, the instruction raises the FLOATING_POINT_EXCEPTION architectural event. Its error-code bitmap contains every cause generated by the operation. The destination, integer FLAGS, and FFLAGS remain unchanged, and arithmetic instructions never modify FSTATUS.

If no generated floating-point exception cause is enabled, the instruction commits its destination and any complete integer FLAGS image defined by the instruction, and ORs every generated cause into FFLAGS. FFLAGS fields not named by the instruction remain unchanged. An instruction-specific rule may exclude a cause.

Comparison, Minimum, and Maximum

FCMP and FTEST write Z,N,C,V as follows.

Relation	Z	N	C	V
greater	0	0	0	0
equal	1	0	0	0
less	0	1	1	0
unordered	0	0	0	1

A quiet NaN produces unordered without NV. A signaling NaN produces unordered and NV. FTEST compares its operand with positive zero under these rules.

For FMIN and FMAX, when exactly one operand is a NaN the numeric operand is the result. When both operands are NaNs, the common NaN-selection rule supplies the result. A signaling NaN generates NV even when the other operand is numeric. Between positive and negative zero, FMIN selects negative zero and FMAX selects positive zero.

Conversions

The final letter of FCVTH, FCVTS, and FCVTD names the H, S, or D format associated with the Fn side of a conversion. The suffix names the other representation. For Fn-to-Fn forms, the source has the suffix format and the destination has the mnemonic format; for example, FCVTS.D converts D to S and FCVTD.H converts H to D. For a form containing one Fn and one Rn or EA operand, Fn has the mnemonic format and Rn or EA has the suffix representation. Source-first operand order therefore permits both directions. The H/D, S/D, or H/S conversion is direct and does not pass through an intermediate floating format.

The .B, .W, .L, and .Q suffixes select 8-, 16-, 32-, and 64-bit integers. FCVTH, FCVTS, and FCVTD interpret those integers as signed; FCVTUH, FCVTUS, and FCVTUD interpret them as unsigned. An Rn integer source uses the selected number of low bits. A signed Rn result is sign-extended to 64 bits and an unsigned result is zero-extended. An EA access transfers exactly the selected number of bytes. Floating-format EA conversion operands are memory operands; floating immediates are not accepted by these forms.

Integer-to-floating and floating-to-floating conversion uses FSTATUS.RM. Floating-to-integer conversion truncates toward zero. A valid conversion that discards a fractional part generates NX. An invalid conversion generates NV without OF or NX. When NV is not enabled, a signed negative overflow or negative infinity produces the least value of the selected signed width, a signed positive overflow or positive infinity produces the greatest value, and NaN produces zero. An unsigned negative value or negative infinity produces zero, positive overflow or positive infinity produces the greatest value of the selected unsigned width, and NaN produces zero.

Conversions generate only NV, OF, UF, and NX; DZ is unchanged. An enabled generated cause raises FLOATING_POINT_EXCEPTION and suppresses the destination write and newly accrued FFLAGS effects. A memory fault likewise suppresses the destination and floating-point state changes.