VSHL

Operation

Logically shifts each active integer element left by its selected-width count.

Assembler Syntax

VSHL.{B|W|L|Q}(z) Pn(p), Vn(v), Vn(w)

VSHL.{B|W|L|Q}(z) Pn(p), imm6(i), Vn(v)

VSHL.{B|W|L|Q}(z) Pn(p), <ea>(e), Vn(v)

VSHL.{B|W|L|Q}(z) Pn(p), Vn(v), <ea>(e)

VSHL.{B|W|L|Q}(z) Pn(p), imm6(i), <ea>(e)

Privilege

Unprivileged

Required CPUID flags

VECTOR

The governing predicate selects active destination elements. An immediate count applies to every active destination element. A vector or memory count source supplies the count from the lane corresponding to that element. VSHL takes the low six bits of each supplied count and reduces the value modulo the selected B, W, L, or Q element width in bits. The resulting count shifts the old destination element to the left and fills vacated low bits with zeros. An effective count of zero writes the original selected-width value for that active element.

With a vector-register destination, active lanes are updated and inactive lanes retain their previous values. A memory destination is updated as an encoded lane-wise read-modify-write: each active element is read, shifted, and written back, while inactive elements retain their previous values.

2.75in