VREVBYTE

Operation

Reverses the byte order within each active element.

Assembler Syntax

VREVBYTE.{W|L|Q}(z) Pn(p), Vn(v)

VREVBYTE.{W|L|Q}(z) Pn(p), <ea>(e), Vn(v)

VREVBYTE.{W|L|Q}(z) Pn(p), Vn(v), <ea>(e)

Privilege

Unprivileged

Required CPUID flags

VECTOR

The register form reads and overwrites each active destination lane. The memory-source form transforms each active memory element and writes it to the corresponding destination lane. An inactive destination lane retains its previous value.

The memory-destination form transforms each active source-register lane and writes it to the corresponding memory element. An inactive memory element remains unchanged. The low-order byte becomes the high-order byte, the next pair exchanges places, and so on; each byte retains its internal bit order.

2.75in

Encodings

VREVBYTE.{W|L|Q}(z) Pn(p), Vn(v)

Format: Instruction format for VREVBYTE.{W|L|Q}(z) Pn(p), Vn(v)

size — allowed: 0x1..0x3 [reserved_vector_element_type]

2.75in VREVBYTE.{W|L|Q}(z) Pn(p), <ea>(e), Vn(v)

Format: Instruction format for VREVBYTE.{W|L|Q}(z) Pn(p), <ea>(e), Vn(v)

size — allowed: 0x1..0x3 [reserved_vector_element_type]

2.75in VREVBYTE.{W|L|Q}(z) Pn(p), Vn(v), <ea>(e)

Format: Instruction format for VREVBYTE.{W|L|Q}(z) Pn(p), Vn(v), <ea>(e)

size — allowed: 0x1..0x3 [reserved_vector_element_type]

dst — excluded: immediate [invalid_destination]