PZIPLO

Operation

Interleave the lower halves of two predicate-lane sequences.

Assembler Syntax

PZIPLO.{B|W|L|Q}(z) Pn(p), Pn(q), Pn(h)

Privilege

Unprivileged

Required CPUID flags

VECTOR

PZIPLO selects the lower half of the significant predicate lanes for the chosen B, W, L, or Q width from each source. In increasing order through those halves, each even result lane receives a left-source value and the following odd result lane receives the corresponding right-source value. The complete destination predicate image is written, and every bit outside its significant positions is cleared. The operation leaves FLAGS unchanged.

PZIPLO.W lower-half predicate interleave

2.75in

Encodings

PZIPLO.{B|W|L|Q}(z) Pn(p), Pn(q), Pn(h)

Format: Instruction format for PZIPLO.{B|W|L|Q}(z) Pn(p), Pn(q), Pn(h)