VNEG

Operation

Negates active integer elements.

Assembler Syntax

VNEG.{B|W|L|Q}(x) Pn(p), Vn(v)

VNEG.{B|W|L|Q}(x) Pn(p), <ea>(e), Vn(v)

VNEG.{B|W|L|Q}(x) Pn(p), Vn(v), <ea>(e)

Privilege

Unprivileged

Required CPUID flags

VECTOR

For each active B, W, L, or Q element, VNEG replaces the element with its selected-width two's-complement negation.

The register form reads and overwrites each active destination lane. The memory-source form reads each active memory element and writes the result to the corresponding destination lane. An inactive destination lane retains its previous value.

The memory-destination form transforms each active source-register element and writes the result to the corresponding memory element. Inactive memory elements retain their previous values, making the destination transaction a lane-wise read-modify-write.

2.75in

Encodings

VNEG.{B|W|L|Q}(x) Pn(p), Vn(v)

Format: Instruction format for VNEG.{B|W|L|Q}(x) Pn(p), Vn(v)

size — allowed: 0x0..0x3 [reserved_vector_element_type]

2.75in VNEG.{B|W|L|Q}(x) Pn(p), <ea>(e), Vn(v)

Format: Instruction format for VNEG.{B|W|L|Q}(x) Pn(p), <ea>(e), Vn(v)

size — allowed: 0x0..0x3 [reserved_vector_element_type]

2.75in VNEG.{B|W|L|Q}(x) Pn(p), Vn(v), <ea>(e)

Format: Instruction format for VNEG.{B|W|L|Q}(x) Pn(p), Vn(v), <ea>(e)

size — allowed: 0x0..0x3 [reserved_vector_element_type]

dst — excluded: immediate [invalid_destination]