Scalable-Vector Floating-Point Instructions

Summary

Scalable-Vector Floating-Point Instructions Summary (Informative)

Mnemonic	Brief description
	Broadcasts a floating-point scalar register to every vector lane.
	Toggles the sign of active floating-point elements.
	Clears the sign of active floating-point elements.
	Computes the square root of each active floating-point element.
	Rounds each active floating-point element to an integral value in the same format using the current rounding mode.
	Rounds each active floating-point element toward zero to an integral value in the same format.
	Rounds each active floating-point element downward to an integral value in the same format.
	Rounds each active floating-point element upward to an integral value in the same format.
	Writes a floating-point classification bitmap for each active element.
	Compares active floating-point lanes and writes a complete predicate image.
	Adds corresponding active floating-point vector elements.
	Subtracts corresponding active floating-point vector elements.
	Multiplies corresponding active floating-point elements.
	Selects the floating-point minimum in each active lane.
	Selects the floating-point maximum in each active lane.
	Divides corresponding active floating-point elements.
	Combines each active destination magnitude with the corresponding source sign bit.
	Converts active half-precision, double-precision, or signed integer elements to single precision.
	Converts active half-precision, single-precision, or signed integer elements to double precision.
	Converts active unsigned integer elements to single-precision floating point.
	Converts active unsigned integer elements to double-precision floating point.
	Converts active floating-point elements to signed longwords.
	Converts active floating-point elements to unsigned longwords.
	Converts active floating-point elements to signed quadwords.
	Converts active floating-point elements to unsigned quadwords.
	Converts active single-precision, double-precision, or signed integer elements to half precision.
	Converts active unsigned integer elements to half-precision floating point.
	Performs fused multiply-add on corresponding active floating-point elements.
	Performs fused multiply-subtract on corresponding active floating-point elements.
	Performs fused negative multiply-add on corresponding active floating-point elements.
	Performs fused negative multiply-subtract on corresponding active floating-point elements.
	Copies one indexed floating-point vector lane to a floating-point scalar register.
	Replaces one indexed vector lane with a floating-point scalar value.
	Reduces active floating-point elements to one scalar sum.
	Reduces active floating-point elements to one minimum value.
	Reduces active floating-point elements to one maximum value.

Vector Floating-Point Element Types and Semantics

VECTORFP requires VECTOR and FP. Its mnemonics use the VF prefix and their element suffixes H, S, and D select IEEE 754 binary16, binary32, and binary64 elements. Binary16 has default quiet NaN 0x7e00. The three-bit tzz selector values five through seven select H/S/D; value four remains invalid. In FP-only families, the two-bit zz selector reserves zero and assigns one through three to H/S/D.

Floating-Point Exceptions, Conversions, and Reductions.

Each active FP lane applies the corresponding scalar rounding, NaN, signed-zero, default-NaN, denormal, and exception rules. Inactive lanes generate no cause. The instruction unions all active-lane causes before testing the enables in the original FSTATUS. If any generated cause is enabled, one FLOATING_POINT_EXCEPTION occurs and neither a destination effect nor newly accrued FFLAGS becomes visible. Otherwise the union is accrued once and all destination effects commit together. FP-to-integer conversion rounds toward zero and follows the scalar saturation and invalid result rules.

FP reductions return an Fn. Empty FP ADD returns positive zero, empty FP MIN returns positive infinity, and empty FP MAX returns negative infinity. FP ADD visits active lanes in increasing logical-lane order and may not be reassociated.