Terminology

Address Values

An effective address (EA) is the address value or operand designator produced by an addressing mode before segment pre-translation. A memory EA produces an address, while register and immediate EAs name register and immediate operands.

A pre-segment virtual address is a virtual-address value before segment pre-translation. Segment pre-translation either converts it to a linear address or reports the architecturally defined fault.

A linear address is the result of segment pre-translation. The page-table walker consumes it when paging is enabled; otherwise the memory system uses it directly.

A physical address is the byte address produced by page-table translation. With paging disabled, the linear address is used directly after the implementation PABITS check.

A memory-system address is the byte address presented to the memory subsystem after every active architectural translation stage.

Normal memory is the coherent memory-location model.

Device memory is the platform-owned physical class that requires MMIO execution rules. A leaf AM selects Normal or MMIO access semantics, while the orthogonal CP field selects one of four cache policies.

Address generation is the instruction-local calculation that combines registers, displacement, index, scale, and immediate fields into an effective address. It does not by itself read memory.

Memory Behavior

A memory access is an individual architectural instruction-fetch, read, or write attempt.

A memory operation is an instruction-level semantic operation that may contain one or more memory accesses or memory events.

A memory event is a read or write unit that participates in coherence or memory ordering.

A memory effect is a result that becomes observable to another logical processor or an external system.

Ordinary is the classification of an operation, such as an ordinary load or store, within the operation taxonomy. Memory type is classified separately.

Segmentation and Paging

Segment pre-translation is the stage between effective-address calculation and paging. A disabled segment passes the EA through. A translated window checks an offset and adds its base, while a bounds-only window checks an already-linear address without adding the base.

A segment register image is the 64-bit architectural value containing the segment base page, size exponent, size mantissa, and bounds-only enable bit.

A disabled segment is a segment with a zero size mantissa. It performs no segment-window check or base addition and passes the effective address through as the linear address.

A translated segment is an enabled segment with bounds-only mode clear. It checks the effective address as an offset within the segment span and then adds the segment base.

A bounds-only segment is an enabled segment with bounds-only mode set. It treats the effective address as already linear and checks only that it lies inside the segment window.

Page-table translation is the optional PTCR.PE-controlled stage that maps a canonical linear address to a physical frame and applies effective permissions, access class, cache policy, and A/D state. Bit 7 is A in both descriptor layouts.

A physical frame number (PFN) is a 16-KiB frame identifier used by leaf page-table entries. An L1, L2, L3, or L4 leaf PTE combines its naturally aligned PFN base with the low 14, 23, 34, or 45 linear-address bits respectively to form a byte address.

Instruction Encoding

An opcode is the value that selects an instruction operation.

The opcode space is the contiguous leading region of an encoded instruction, from byte 0 through the byte immediately before the first payload. It includes the header and may contain operand or control fields in addition to the opcode.

The header is the leading byte range within the opcode space that determines the encoded instruction length and opcode-space selection. It is the first byte for extrashort and short instructions and the first two bytes for medium and longer instructions.

A payload is an independently determined unit after the opcode space that supplies additional information and increases the required instruction length. Adjacent units are separate payloads when their presence, length, or meaning is determined independently.

A field is a defined bit region within the opcode space or a particular payload. An undivided payload may carry its value without defining a separate field.

The required instruction length is the opcode-space length plus the length of every payload. It excludes padding.

The encoded instruction length is the required instruction length plus any trailing padding in the encoded record.

Padding is trailing encoded-record content that carries no information. Payload accounting excludes padding.

Control Flow

A near control transfer is a CALL, RET, JMP, or conditional branch that changes only PC within the current code-segment context.

A segment-changing control transfer is a transfer that updates CS and PC in one architectural commit. Long jumps, long calls, and long returns belong to this category.

Long Call is the instruction family that creates a two-value return context while changing the code segment and program counter.

Long Jump is the instruction family that changes the code segment and program counter without creating a return context.

Long Return is the instruction family that consumes a two-value return context to restore the code segment and program counter.

A long return frame is the two-value return context created by Long Call and consumed by Long Return.

Tracing Terms

The TRACE instruction is the marker instruction that records its immediate marker and current instruction boundary in the implementation trace stream when that stream is enabled.

A trace unit is the execution-completion unit sampled by STATUS.TF.

SINGLE_STEP is the architectural event delivered after successful completion of a TF-selected trace unit when RF does not suppress the automatic debug stop.

Architectural State

A logical processor is an architecturally independent execution context that owns its architectural state and remains the architectural execution subject.

A thread is a software execution context that may execute on a logical processor.

A general-purpose register is one of the sixteen 64-bit registers R0 through R15.

An Rn register is a general-purpose register selected through the four-bit Rn operand namespace. It may hold integers, addresses, counters, selectors, or temporary data according to the instruction encoding.

The stack pointer register is SP. It lies outside the four-bit Rn namespace and uses SS as the fixed segment for SP-relative addressing.

A segment register operand is a 64-bit segment register exposed through the SREG operand class. The SREG selector table maps its eight encodings to DS, SS, and GS0 through GS5. RDSEG CS and PUSH CS read the current CS image through their fixed CS encodings.

A state register is named architectural state such as FLAGS or STATUS. RDFLAGS, WRFLAGS, RDSTATUS, and WRSTATUS access these registers.

A control register is a privileged register exposed through the CR operand class, such as PTCR, ASCR, ECR, EPC, UCTL, and UINFO.

Architectural state is programmer-visible current state.

A register image is the complete bit representation read from or written to one register.

A processor-state image is an aggregate representation of multiple architectural-state components, such as a reset-state table.

Processor state is the complete architectural state set of a logical processor.

A temporary operand-evaluation state is a working copy used during operand evaluation.

The program counter is the architectural state object that selects instruction execution.

An instruction address is the numeric address of an instruction.

A continuation is a saved or selected resumption point.

Architectural Exceptions

An architectural exception is a synchronous architectural event delivered as a fault or trap.

Floating-Point and Architectural Exceptions

A floating-point exception condition is an IEEE-754 condition such as NV, DZ, OF, UF, or NX. An enabled condition raises the FLOATING_POINT_EXCEPTION architectural event before the instruction commits the effects suppressed by that event.

A floating-point exception flag is the accrued FFLAGS bit corresponding to a floating-point exception condition.

Vector Architectural State

A vector register is one of the 32 VLEN-bit registers V0 through V31.

A predicate register is one of P0 through P15 and contains one governing bit for each byte of a vector register.

A logical vector lane is one selected-width element. Predicate bit iE governs lane i for an E-byte element. VLEN is the reset-stable implementation-selected vector register width in bits.

Normative Qualifiers

Reserved is a classification meaning that software must not depend on the field's value or behavior.

Must be zero is a requirement that software write zero.

Read-as-zero is a rule under which reads return zero while the field remains reserved.

Ignored is a rule under which hardware accepts the field without using it for the current operation.

Preserved is a requirement that software retain the previous value when rewriting the containing object.

Software-defined state is state reserved for software use. Hardware interpretation is limited to behavior explicitly defined by the containing structure.

Implementation-defined behavior is behavior selected by the implementation and published through CPUID, platform documentation, or firmware.

An illegal use is use of an opcode, effective-address form, selector, or operation that raises the exception named by the defining rule.